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研究生:李朝民
研究生(外文):Chao-Min Li
論文名稱:左到右陣列乘法器之分析與比較
論文名稱(外文):The analysis and comparison of the left to right array multipliers
指導教授:田子坤
指導教授(外文):Tzu-Kun Tien
學位類別:碩士
校院名稱:南台科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:中文
論文頁數:60
中文關鍵詞:左到右陣列乘法器分裂混合
外文關鍵詞:left to right array multipliersplithybrid
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在數位信號處理器(digital signal processors)中,乘法器(multiplier)是不可或缺之主要關鍵電路且決定系統之效能,這是因為不管是在電路的延遲時間(delay time)、面積(area)、或是功率消耗(power dissipation),乘法器元件都是最為顯著的。乘法器之種類繁多,而陣列乘法器較為普遍之一種。然而一般之陣列乘法器在做部分乘積之加法時因信號傳遞時間不一致而造成glitch效應,因而增加功率之消耗。
在本篇論文中我們提出一個混合分裂式左到右陣列乘法器電路架構,以減少加法器陣列中glitch效應和電路中電晶體的轉態(switching activity)次數,此混合式左到右陣列乘法器結合了蛙跳式(leapfrog)及分裂式(split)架構方式之優點來減少因glitch效應所造成之功率上的無謂消耗。另外我們也利用了偵測數值動態範圍(detecting effective dynamic range)之方式來減少電路中電晶體轉態次數(switching activity)以節省在部份乘積中無效的部分所造成的功率消耗。我們以細胞元基礎的設計流程(cell-based design flow),及使用CIC提供之TSMC台積電0.35μm CMOS technology之細胞元庫(cell library)驗證我們的乘法器電路,在經比較近年來發表的左到右陣列乘法器之各項效能指標後,實驗結果顯示我們的乘法器電路具有最低消耗功率及小面積之優點。
In a digital signal processor, the multiplier plays a major role in the processor not only for the circuit delay but also for the power consumption. There are many kinds of multipliers; array multipliers are very popular due to property of regular structure. However, array multipliers may consume more power when the glitch effect exists in the circuit.
In the thesis, we have proposed a new design method of hybrid left to right array multiplier to reduce the glitch effect and the switching activities. The new multiplier combines the properties of the leapfrog and split multipliers to the glitches in the circuit and then the power consumption can be reduced. The new multiplier also adopts the dynamic range detection method to lower switching activities during the addition of partial products. We have implemented the new multiplier by using the cell-based design method with a TSMC 0.35μm cell library. The experimental results show that our new multiplier has the advantages of low power and high speed properties.
摘 要 iv
Abstract v
誌  謝 vi
目 次 vii
表目錄 ix
圖目錄 x
第一章緒論 1
1.1 前言 1
1.2 目前乘法器之相關研究 1
1.3 研究動機 3
1.4 章節概論 4
第二章乘法器相關研究 5
2.1 串並式乘法器 5
2.2陣列式乘法器 7
2.3樹狀式乘法器 8
2.3.1 壓縮樹 10
2.3.2 最終加法器 13
2.4 布斯編碼 15
2.5左到右陣列乘法器相關研究 20
2.5.1傳統左到右陣列乘法器 20
2.5.2蛙跳式架構左到右陣列乘法器 22
2.5.3分裂蛙跳式架構左到右陣列乘法器 25
第三章混合分裂式乘法器電路設計與硬體實現 28
3.1前言 28
3.2乘法器動態範圍單元設計 32
3.3布斯混合編碼設計考量 34
3.4上下分裂蛙跳式架構 38
第四章實驗與模擬結果 40
4.1測試方法 41
4.2實驗結果 42
第五章結論 47
參考文獻 48
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[2] 詹政勳,具低功率高效能之乘法相關運算元件自動合成器,國立中正大學資訊工程學系研究所碩士論文,民91年

[3] H. H. Yao, E. E. Swartzlander, Jr.,”Serial-parallel multipliers, ” IEEE Conference
on Signals, Systems and Computers, vol.1, 1993. Page(s):359 – 363

[4] H. I. Saleh, A. H. Khalil, M. A. Ashour, A. E. Salama, “Novel serial-parallel multipliers, ” IEEE Journal on Circuits, Devices and Systems, Vol.148, 2001 Page(s):183 - 189

[5] S. S. Kidambi, F. El-Guibaly, and A. Antoniou,“Area-efficient multipliers for digital signal processing applications,” IEEE Journal on Circuits and Systems II: Analog and Digital Signal Processing, Vol 43, 1996, Page(s):90 – 95

[6] Lan-Da Van, Shuenn-Shyang Wang, Tenqchen Shing,Wu-Shiung Feng, and Bor-Shenn Jeng, “Design of a lower-error fixed-width multiplier for speech processing application,” IEEE Conference on Circuits and Systems, Vol.3, 1999, Page(s):130 - 133.

[7] Kwang, H.-L. and Chong, S.-R., “A Hardware Reduced Multiplier for Low Power Design”, IEEE Conference on ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific, 2000, Page(s):331 - 334

[8] Booth, A.-D., “A Signed Binary Multiplication Technique,” Quartery J. Mechanical Application in Math., vol. 4, part 2, pp. 236-240, 1951

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Computers, vol 13, pp.14-17, 1964

[10] L. Dadda, “Some Schemes for Parallel Multipliers,” Alta Frequenza, vol. 34,
pp. 349-356, 1965

[11] K. C. Bickerstaff, E. E. Jr. Swartzlander, M. J. Schulte, “Analysis of column compression multipliers,” IEEE Conference on Computer Arithmetic, 2001, Page(s):33 – 39

[12] K. Prasad, K. K. Parhi, “Low-power 4-2 and 5-2 compressors,” IEEE Conference on Signals, Systems and Computers, Vol. 1, 2001, Page(s):129 - 133

[13] A. Wu, C. K. Ng, K.C. Tang, “Modified Booth pipelined multiplication,” IEEE Journal on Electronics Letters, Vol. 34, 1998, Page(s):1179 – 1180

[14] M. Michael Vai, “VLSI DESIGN”, CRC PRESS, 2000

[15] M. D. Ercegovac, T. Lang , “Fast Multiplication Without Carry-Propagate Addition,” Journal on Computers, IEEE Transactions, Vol 39., Issue 11, Nov. 1990 Page(s):1385 - 1390

[16] S.S. Mahant-Shetti, P.T. Balsara, C. Lemonds, “High performance low power array multiplier using temporal tiling,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 7, NO1, March 1999
[17] Zhijun Huang, M. D. Ercegovac, “High- performance low-power left-to-right array multiplier design,” IEEE Transactions on Computers, vol. 54 , NO. 3 , March 2005

[18] 沈志堅,應用於多媒體計算之低功率乘法器累加器,國立中正大學電機工程研究所碩士論文,民92年

[19] B.S. Cherkauer, E.G. Friedman, “A hybrid radix-4/madix-8 low power signed multiplier architecture,” IEEE Transactions on Circuits and Systems, Analog and Digital Signal Processing, vol. 44 , NO. 8 , August 1997
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