臺灣博碩士論文加值系統

唯讀記憶體（ROM）常被應用於ASIC設計中且佔有重要之一環。然而一般之唯讀記憶體的設計大多採用全客戶設計，因此設計時間及成本也較高，針對這個缺點，我們提出一個可對唯讀記憶體做全自動化設計之編譯器，我們的唯讀記憶體編譯器包含兩個主要部分：編譯器及細胞元庫設計。在編譯器設計部分，我們使用PERL及SKILL語言針對唯讀記憶體做分析，以決定電路各部分之元件的最佳尺寸並產生可自動產生唯讀記憶體佈局圖之檔案輸出，在細胞元庫設計部份，我們建立以下唯讀記憶體區塊的leaf cell：列解碼器、行解碼器、核心陣列、時脈緩衝器和字線緩衝器等等。我們針對唯讀記憶體電路各個部分建立不同元件尺寸的細胞元，及做細胞元時序分析以提供編譯器產生最符合設計規則之唯讀記憶體佈局圖。
編譯器在產生佈局圖後，我們也將電路之netlist檔和layout檔作LVS驗證。除了驗證佈局電路之DRC、LVS外，我們也萃取電路之寄生電容做Post-simulation，實驗結果證明編譯器所產生之佈局電路符合規則設計。

Read only memories (ROM) are often used to store constant data and play a major role in ASICs. However the designs of read only memories mostly adopt the full custom design method, there are relatively high for the designing period and cost. Against these shortcomings, we have designed a ROM compiler that can automatically generate the layout of a ROM according to the input of a ROM table. Our ROM compiler system includes two main parts; the compiler and the leaf cell library. In the design of complier, we have used PERL and SKILL languages to design the compiler. The compiler can analyze an input ROM table to decide the uses of leaf cells in the library to generate the layout, and therefore the performance of the ROM can be guaranteed to meet the specification of the design. In the design of leaf cells, we have partitioned the ROM circuit into five major parts: the row decoder, word-line buffer, core array, column decoder, and clocked buffer.
In each part of the ROM circuit we have designed a number of leaf cells with different driving abilities by using the technology of TSMC 0.18 um. All the leaf cells in the library are designed and analyzed to meet the timing constraints, design requirements and design rules. Besides the DRC checking for a layout generated by our ROM compiler, we have performed LVS to confirm the correction of the design.

摘　要...........................................iv
Abstract.........................................v
誌　謝...........................................vi
目　次...........................................vii
表目錄...........................................ix
圖目錄...........................................xi
第一章 簡介.......................................1
1.1 前言..........................................1
1.2 唯讀記憶體設計考量..............................2
1.3 唯讀記憶體相關研究探討..........................4
1.4 本論文之研究方向...............................5
1.5 論文章節安排...................................6
第二章 唯讀記憶體架構分析...........................7
2.1 唯讀記憶體基本架構..............................7
2.2 列解碼器.......................................8
2.2.1 列解碼器電路設計型態..........................9
2.2.2 NAND type列解碼器...........................10
2.2.3 NOR type列解碼器............................11
2.2.4 Pass Transistor型態列解碼器..................12
2.3 列解碼器......................................14
2.3.1 Pass Transistor行解碼器.....................14
2.3.2 Tree type行解碼器...........................15
2.3.3 動態PLA型態行解碼器..........................16
2.4 核心陣列......................................16
2.4.1 NAND type核心陣列...........................17
2.4.2 NOR type核心陣列............................18
2.4.3 Hierarchical type核心陣列...................19
2.5 字線緩衝器....................................20
2.6 時脈緩衝器....................................21
第三章　唯讀記憶體編譯器設計與實現....................23
3.1 唯讀記憶體編譯器系統............................23
3.1.1 相關著作....................................23
3.1.2 唯讀記憶體編譯器規格..........................23
3.2 唯讀記憶體編譯器設計............................27
3.2.1 唯讀記憶體編譯器設計考量......................28
3.3 佈局平面規劃...................................29
3.4 唯讀記憶體編譯器之leaf cell設計.................30
3.5 唯讀記憶體的leaf cell library..................37
3.6 佈局圖之SKILL Code產生.........................40
3.6.1 SKILL code常用function......................40
第四章　實驗結果....................................43
4.1 各個leaf cell之延遲測量.........................43
4.2 唯讀記憶體電路實現..............................46
4.3 可靠度與正確度分析..............................48
第五章　結論........................................51
參考文獻............................................52

[1] Byung-Do Yang and Lee-Sup Kim, “A Low-Power ROM Using Charge Recycling and Charge Sharing Techniques,” IEEE Journal of solid-state circuits, vol.38, NO.4, April 2003.

[2] Byung-Do Yang and Lee-Sup Kim,” A low-power charge-recycling ROM architecture,” IEEE Transactions on very large scale integration (VLSI) systems, vol.11, NO.4, August 2003.

[3] Cheng-Hui Yang, “Circuit and Compiler Design of Mask ROMs for High-Speed and Low-Power ASIC Applications”, July 2000.

[4] Bei-Ying Chen, “An Area-Saving ROM Decoder”, June 2000.

[5] E.de Angel. Earl E. Swartdander. Jr. “Survey of Low Power Techniques for ROMs”. International Symposium on Low Power. Electronics arid Design. 1997. Pages 7-11.

[6] Barry R. L. et al. “A High-Performance ROM Compiler for 0.50um and 0.36um CMOS Technologies,” ASIC Conference and Exhibit, 8th IEEE international, pp.370-373, 1995.

[7] Tony Tsang, “A compliable Read-Only-Memory Library for ASIC Deep Sub-micron Applications”, IEEE 1997.

[8] M. M. Khellah and M. I. Elmasry, “Low-power design of high-capacitive CMOS circuits using a new charge sharing scheme,” in Proc. IEEE Int. Solid-State Circuits Conf., 1999, pp. 286–287.

[9] Ching-Rong Chang, Jinn-Shyan Wang, and Cheng-Hui Yang “Low-Power and High-Speed ROM Modules for ASIC Applications” IEEE Journal of solid-state circuits, vol.36, NO.10, October 2001.

[10] S. Padoan and A.Boni“High speed, low power, low voltage ROMs”Dipartimento di Ingegneria dell'Informazione Universith degli Studi di Parma.

[11] Ching-Rong Chang, Student Member, IEEE, Jinn-Shyan Wang, Member, IEEE, and Cheng-Hui Yang,” Low-Power and High-Speed ROM Modules for ASIC Applications”, IEEE Journal of solid-state circuits, vol.36, NO.10, October 2001.

[12] C.-R. Chang and J.-S. Wang,” A new high-speed/low-power dynamic CMOS logic and its application to the design of an AOI-type ROM,”in Proc. IEEE Int. Symp. Circuits and Systems, 1999, pp. 1254–1257.

[13] R. H. Krambeck, C. M. Lee, and H.-F. S. Law,” High speed compact circuits with CMOS,”IEEE J. Solid-State Circuits, vol. SC-17, pp. 614–619, June 1982.

[14] Byung-Do Yang and Lee-Sup Kim,” Low-power charge-sharing ROM using dummy bit lines”, Electronics Letters 70th July 2003 Vol. 39 No. 14.

[15] Alfred0 R. Linz, Member,” A Low-Power PLA for a Signal Processor” IEEE Journal of solid-state circuits, vol.26, NO.2, February 1991.

[16] Yoshihisa Iwata, Masaki Momodomi, Tomoharu Tanaka, Hideko Oodaira, Yasuo Itoh, Ryozo Nakayama, Seiichi Aritome, Tetsuo Endoh, Riichiro Shirota, Kazunori Ohuchi, and Fujio Masuoka, Associate member,” A High-Density NAND EEPROM with Block-Page Programming for Microcomputer Applications” IEEE Journal of solid-state circuits, vol.25, NO.2, April 1990.

[17] Wu; Cheng; Kua-Hsing,”CMOS dynamic logic structure. ”5378942, Appl. No. 71523, U.S.A. Pantent, Jun.3 1993

[18] Ching-Rong Chang and Jinn-Shyan Byung-Do Yang and Lee-Sup Kim,” A low power charge recycling ROM architecture,” in Proc. IEEE Int. Circuits Systems Symp., 2001, pp. 510–513.

[19] X. Q. Zhang, T. Tsang, and D. Mehta, “A multi-megabit memory compiler tomorrow's IP”, Electrical and Computer Engineering, IEEE Canadian Conference, vol. 1 , pp. 538 – 542, May 1999.

[20] T. Sunaga, "A 30-ns cycle time 4-Mb mask ROM," IEEE J. of Solid-State Circuits, vol. 29, NO.11, pp. 1353-1358, Nov. 1994.