|
REFERENCES [1]J. J. Liou, A. Ortiz-Conde, and F. Garcia-Sanchez, “Analysis and Design of MOSFETs Modeling, Simulation, and Parameter Extraction”, Kluwer Academic Publishers. [2]J. S. Yuan and J. J. Liou, “Semiconductor Device Physics and Simula-tion,”Plenum Publishing Corporation, May, 1998. [3]G. Baccarani and S. Reggiani, “A compact double-gate MOSFET model comprising quantum-mechanical and nonstatic effects,” IEEE Trans. Electron Devices, vol. 46, Issue: 8 , Aug., 1999, pp. 1656 – 1666. [4]T. K. Chiang, “An analytical (classical) subthreshold behavior models for the symmetrical fully-depleted SOI double-gate MOSFET,” is ac-cepted by Journal of the Chinese Institute of Engineers for 2003. [5]X. Liu, J. Kang, L. Sun, R. Han, and Y. Wang, “Threshold voltage model for MOSFETs with high-k gate dielectrics,” IEEE Electron Device Lett., vol.23 , Issue: 5 , May, 2002, pp.270 – 272. [6]T. Tonaka, H. Horie, S. Ando, and S. Hijiya, “Analysis of p+ poly Si-double-gate thin-film SOI MOSFETS,” in IEDM Tech. Dig.,1991, pp. 683-686. [7]J. Brini, M. Benachir, G. Ghibaudo, and F. Balestra, “Threshold voltage and subthreshold slope of the volume-inversion MOS transistor,” in Proc. Inst. Elect. Eng.,vol. 138, 1991, pp. 133-136. [8]D. J. Frank, S. E. Laux, and M. V. Fischetti, “Monte Carlo simulation of a 30nm dual-gate MOSFET: How short can Si go?,” in IEDM Tech. Dig., 1992, pp.553-556. [9]S. Venkatesan, G. W. Neudeck, and R. F. Pierret, “Dual-gate operation and volume inversion in n-channel SOI MOSFET’s,” IEEE Electron De-vice Lett., vol. 13,1992, pp. 44-46. [10]R.-Y. Yan, A. Ourmazd, and K. F. Lee, “Scaling the Si MOSFET: From bulk to SOI to bulk,” IEEE Trans. Electron Devices, vol. 39, 1992, pp. 1704-1710. [11]K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, and Y. Arimoto, “Scaling theory for double-gate SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 40, 1993, pp.2326-2329. [12]K.-W. Su and J. B. Kuo, “A nonlocal impact ionization/lattice tempera-ture model for VLSI double-gate ultrathin SOI NMOS devices,” IEEE Trans. Electron Devices, vol. 44, 1997, pp. 324-330. [13]K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, Y. Arimoto, and T. Ito, “Analytical surface potential expression for thin-film double-gate SOI MOSFET’s,” Solid-State Electron., vol. 37, 1994, pp. 327-332. [14]T. Tanaka, K. Suzuki, H. Horie, and T. Sugii, “Ultrafast operation of Vth-adjusted p+-n+ double-gate SOI MOSFET’s,” IEEE Electron De-vice Lett., vol. 15,1994, pp. 386-388. [15]K. Suzuki, T. Tanaka, and T. Sugii, “Analytical threshold voltage model for short channel n+-p+ double-gate SOI MOSFET’s,” IEEE Trans. Electron Devices, vol.43,1996, pp. 732-737. [16]S. H. Tang, P. Xuan, J. Bokor, and C. Hu, “Comparison of short-channel effect and offstate leakage in symmetric vs. asymmetric double gate MOSFETs,”2000 IEEE International SOI Conference, 2-5 Oct., 2000, pp. 120 – 121. [17] H.-S. P. Wong, D. J. Frank, and P. M. Solomon, “Device design con-siderations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation,” Electron De-vices Meeting, 1998. '98 International IEDM Technical Digest., 6-9 Dec., 1998, pp. 407 – 410. [18]L. Chang, S. Tang, T.-J. King, J. Bokor, and C. Hu, “Gate length scaling and threshold voltage control of double-gate MOSFETs,” Electron De-vices Meeting, 2000. International, IEDM Technical Digest. 10-13 Dec., 2000, pp. 719 – 722. [19]X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E.Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor,and C. Hu, “Sub 50-nm FinFET: PMOS,” Electron De-vices Meeting, 1999. International, IEDM Technical Digest. 5-8 Dec., 1999, pp. 67 – 70. [20]D. J. Frank, S. E. Laux, and M.V. Fischetti, “Monte Carlo simulations of p- and n-channel dual-gate Si MOSFET's at the limits of scaling,” Elec-tron Devices, IEEE Transactions on , Volume: 40 , Issue: 11 , Nov., 1993, pp. 2103. [21]Y. Tosaka, K. Suzuki, and T. Sugii, “Scaling-parameter-dependent model for subthreshold swing S in double-gate SOI MOSFET's,” IEEE Electron Device Letters, , vol. 15 , Issue: 11 , Nov., 1994, pp. 466 – 468 [22]H.-S. P. Wong, D. J. Frank, Y. Taur, and J. M. C. Stork, “Design and performance considerations for sub-0.1 m double-gate SOI MOSFETs,” in IEDM Tech. Dig., 1994, pp. 747-750. [23]T. Su, J. P. Denton, and G. W. Neudeck, “New planar self-aligned dou-ble fully depleted P-MOSFETs using epitaxial lateral over-growth (ELO) and selectively grown source/drain (S/D),” in IEEE Int. SOI Conf., Oct., 2000, pp. 110-111. [24]J.-H. Lee, G. Taraschi, A. Wei, T. A. Langdo, E. A. Fitzgerald, and D. A. Antoniadis, “Super self-aligned double (SSDG) MOSFETs utilizing oxidation rate difference and selective epitaxy,” in IEDM Tech. Dig., 1999, pp. 71-74. [25]H.-S. P. Wong, K. K. Chan, and Y. Taur, “Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel,” in IEDM Tech. Dig., 1997, pp. 427-430. [26]D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, R.Anderson, T.-J. King, J. Bokor, and C. Hu, “FinFET –a self-aligned double-gate MOSFET scalable to 20 nm,” IEEE Trans. Electron Devices, vol. 47, Dec., 2000, pp. 2320-2325. [27]D. M. Fried, A. P. Johnson, E. J. Nowak, J. H. Rankin, and C. R. Willets, “A sub-40 nm body thickness N-type FinFET,” in Proc. Device Res. Conf., 2001, pp. 24-25. [28]X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, R.Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, “Sub-50 nm P-channel FinFET,” IEEE Trans. Electron Devices, vol. 48, May, 2001, pp. 880-886. [29]Y.-K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T.-J. King, J.Bokor, and C. Hu, “Sub-20 nm CMOS FinFET technolo-gies,”Electron Devices Meeting, 2001. International IEDM Technical Digest. 2-5 Dec.,2001, pp. 19.1.1 - 19.1.4. [30]J. Kedzierski, D.M. Fried, E. J. Nowak, T. Kanarsky, J. H. Rankin, H. Hanafi,W. Natzle, D. Boyd, Y. Zhang, R. A. Roy, J. Newbury, C. Yu, Q. Yang, P. Saunders, C.P. Willets, A. Johnson, S. P. Cole, H. E. Young, N. Carpenter, D. Rakowski, B. A.Rainey, P. E. Cottrell, M. Ieong, and H.-S. P. Wong, “High-performance symmetric-gate and CMOS-compatible Vt asymmetric-gate FinFET devices,” Electron Devices Meeting, 2001. In-ternational, IEDM Technical Digest. , 2-5 Dec., 2001, pp.19.5.1 - 19.5.4. [31]Y.-K. Choi, T.-J. King, and C. Hu, “Spacer FinFET: nano-scale CMOS technology for the terabit era,” 2001 International Semiconductor Device Research Symposium, 5-7 Dec., 2001, pp. 543 – 546. [32]S. H. Tang, L. Chang, N. Lindert, Y.-K. Choi, W.-C. Lee, X. Huang, V.Subramanian, J. Bokor, T.-J. King, and C. Hu, “FinFET-a quasi-planar double-gate MOSFET,” Solid-State Circuits Conference, 2001. Digest of Technical Papers.2001 IEEE International, ISSCC. 5-7 Feb., 2001, pp. 118 - 119, 437. [33]N. Lindert, Y.-K. Choi, L. Chang, E. Anderson, W.-C. Lee, T.-J. King, J.Bokor, and C. Hu, “Quasi-planar FinFETs with selectively grown ger-manium raised source/drain,”2001 IEEE International, SOI Conference, 1-4 Oct., 2001, pp. 111 – 112. [34]E. Liu; C. Lin; X. Liu; and R. Han, “Simulation of 100nm SOI MOSFET with FINFET structure,”2001 Solid-State and Integrated-Circuit Tech-nology. Proceedings on 6th International Conference, vol. 2, 22-25 Oct., 2001, pp. 883 – 886. [35]F.-L. Yang, H.-Y. Chen, F.-C. Chen, Y.-L. Chan, K.-N. Yang, C.-J. Chen, H.-J.Tao, Y.-K. Choi, M.-S. Liang, and C. Hu, “35 nm CMOS FinFETs,” VLSI Technology,2002. Digest of Technical Papers. 2002 Symposium on , 11-13 June 2002, pp. 104 –105. [36]J. G. Fossum, M. M. Chowdhury, V. P. Trivedi, T.-J. King, Y.-K. Choi, J. An, and B. Yu, “Physical insights on design and modeling of nanoscale FinFETs,” Electron Devices Meeting, 2003. IEEE International, IEDM '03 Technical Digest. 8-10 Dec., 2003, pp. 29.1.1 - 29.1.4. [37]M. Kondo, R. Katsumata, A. Hideaki, T. Hamamoto, S. Ito, N. Aoki, and T.Wada, “A FinFET design based on three-dimensional process and de-vice simulations,”Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. International Conference on, 3-5 Sept., 2003, pp. 179 – 182. [38]G. Pei, J. Kedzierski, P. Oldiges, M. Ieong, and E.C.-C. Kan, “FinFET design considerations based on 3-D simulation and analytical modeling,” IEEE Transactions on Electron Devices, vol. 49, Issue: 8, Aug., 2002, pp. 1411 – 1419. [39]C. P. Auth and J. D. Plummer, “A simple model for threshold voltage of surrounding-gate MOSFET's,” IEEE Transactions on Electron Devices, vol.45, Issue: 11 , Nov., 1998, pp. 2381 – 2383. [40]S.-H. Oh, D. Monroe, and J.M. Hergenrother, “Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, sur-rounding-gate MOSFETs,” IEEE Electron Device Letters, vol. 21, Issue: 9, Sept., 2000, pp. 445 – 447. [41]A. Kranti, S. Haldar, and R. S. Gupta, “A two-dimensional analytical model for thin film fully depleted surrounding gate (SGT) MOSFET,” Microwave Conference, 2000 Asia-Pacific , 3-6 Dec., 2000, pp. 880 – 883. [42]C. P. Auth and J. D. Plummer, “Vertical, fully-depleted, surrounding gate MOSFETs on sub-0.1 μm thick silicon pillars,” Digest. 54th Annual, Device Research Conference, 1996. 24-26 June, 1996, pp. 108 – 109. [43]Y. Taur, L. H. Wann, and D. J. Frank,”25 nm CMOS design considera-tions,” in IEDM Tech. Dig., 1998, pp.789-792 [44]Y. Taur, D. A. Buchanan, W. Chen, D.J. Frank, K.E. Ismail, S.-H Lo, G. A. Sai-Halasz, R. G. Viswanathan, H.-J.C. Wann, S.J. Wind, and H.-SP. Wong, ”CMOS scaling into the nanometer regime,” Proc. IEEE,vol.85, 1997, pp.486-504. [45]D. J. Frank, R. H. Dennard, and E. Nowak,”Device scaling limits of Si MOSFETs and their application dependences,” Proc. IEEE,vol.89, 2001, pp.259-288. [46]Y. Taur,”CMOS scaling beyond 0.1 :how short can Si go?,”in Proc. Symp. VLSI Technology, 1999, pp.6-9. [47]C. H. Wang, K. Noda, T. Tanaka, M. Yoshida, and C. Hu,”A compara-tive study of advanved MOSFET concepts,” IEEE Trans. Electron De-vices, vol.43, 1996, p.1742-1753. [48]D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, T.-J. King, J Bokor, and C. Hu,”A folded-channel MOSFET for deep-sub-micro era,” in IEDM Tech. Dig., 1998, pp.1032-1034. [49]D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, T.-J. King, J Bokor, and C. Hu,”FinFET-A self-aligned double-gate MOSFET scalable to 20nm,” IEEE Trans. Electron devices, vol. 47, 2000, pp.2320-2325. [50]X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y. K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu,”Sub-50nm FinFET:PMOS,” in IEDM Tech. Dig., 1999, pp. 67-70. [51]X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y. K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu,”Sub-50nm P-channel FinFET,” IEEE Trans. Electron Device,vol.48, 2001, pp.880-886. [52]D. M. Fried, A.P. Johnson,E.J. Nowak, J.H. Rankin, C.R. Willets,”A sub-40 nm body thickness N-type FinFET,” in Proc. Device Res. Conf.,2001 pp.24-25. [53]Yang-Kyu Choi, Tsu-Hae King, and C. Hu,”Nanoscale CMOS Spacer FinFET for the Terabit Era,”IEEE Electron device Letter, vol.23, 2002, pp.25-27. [54]N. Lindert, L. Chang, Y.-K. Choi, E. H. Anderson, W.-C. Lee, T.-J. King, J. Boker, and C. Hu,”Sub-60nm Quasi-planar FinFETs fabricated using a simplified process,”IEEE Trans Electron Devices, vol.22, 2001, pp.487-489. [55]Y.-K. Choi, N. Lindert, P.Xuan, S. tang, D. Ha, E. Anderson, T.-J. King, J.Bokor, and C. Hu,”Sub-20nm CMOS FinFET Technology,” in IEDM Tech. Dig, 2001, pp.421-424. [56]Pei, G.; Kedzierski, J.; Oldiges, P.; Ieong, M.; Kan, E.C.-C, “FinFET de-sign considerations based on 3-D simulation and analytical model-ing” IEEE Transactions on Electron Devices, vol. 49 Issue: 8 , Aug., 2002, pp. 1411 -1419. [57]X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, R. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, “Sub-50 nm P-channel FinFET,” IEEE Trans. Electron Devices, vol. 48, May, 2001, pp. 880–886. [58]X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, R. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, “Sub-50 nm P-channel FinFET,” IEEE Trans. Electron Devices, vol. 48, May, 2001, pp. 880–886. [59]Te-Kuang Chiang., “The modeling of the short channel devices in deep- submicrometer range: including GaAs MESFET's, Si-SOI MESFET's, SOI MOSFET's and double-gate SOI MOSFET's” ph. D. dissertation, Department of Electrical Engineering, National Cheng-Kung University, R.O.C. , 1998. [60]C. H. Wann, K. Noda, T. Tanaka, M. Yoshida, and C. Hu, “A compara-tive study of advanced MOSFET concepts,” IEEE Trans. Electron De-vices, vol. 43, no. 10,Oct., 1996, pp. 1742-1753. [61]Y.-K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T.-J. King, J.Bokor, and C. Hu, “Sub-20 nm CMOS FinFET technolo-gies,”Electron Devices Meeting, 2001. International, IEDM Technical Digest. 2-5 Dec, 2001, pp. 19.1.1 - 19.1.4. [62]J. Kedzierski, D. M. Fried, E. J. Nowak, T. Kanarsky, J. H. Rankin, H. Hanafi, W. Natzle, D. Boyd, Y. Zhang, R. A. Roy, J. Newbury, C. Yu, Q. Yang, P. Saunders, C.P. Willets, A. Johnson, S. P. Cole, H. E. Young, N. Carpenter, D. Rakowski, B. A.Rainey, P. E. Cottrell, M. Ieong, and H.-S. P. Wong, “High-performance symmetric-gate and CMOS-compatible Vt asymmetric-gate FinFET devices,” Electron Devices Meeting, 2001. In-ternational, IEDM Technical Digest. , 2-5 Dec., 2001, pp.19.5.1 - 19.5.4. [63]Y.-K. Choi, T.-J. King, and C. Hu, “Spacer FinFET: nano-scale CMOS technology for the terabit era,” 2001 International, Semiconductor De-vice Research Symposium, 5-7 Dec., 2001, pp. 543 – 546. [64]S. H. Tang, L. Chang, N. Lindert, Y.-K. Choi, W.-C. Lee, X. Huang, V. Subramanian, J. Bokor, T.-J. King, and C. Hu, “FinFET-a quasi-planar double-gate MOSFET,”2001 IEEE International Solid-State Circuits Conference, 5-7 Feb., 2001, pp. 118 - 119. [65]N. Lindert, Y.-K. Choi, L. Chang, E. Anderson, W.-C. Lee, T.-J. King, J. Bokor, and C. Hu, “Quasi-planar FinFETs with selectively grown ger-manium raised source/drain,” IEEE International , SOI Conference, 1-4 Oct., 2001, pp. 111 – 112. [66]D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, T.-J. King, J. Bokor, and C. Hu, “A folded-channel MOSFET for deep-sub-micro era,” in IEDM Tech. Dig., 1998, pp. 1032-1034. [67]X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, R.Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, “Sub-50 nm P-channel FinFET,” IEEE Trans. Electron Devices, vol. 48, May, 2001, pp. 880-886. [68]D. M. Fried, A. P. Johnson, E. J. Nowak, J. H. Rankin, and C. R. Willets, “A sub-40 nm body thickness N-type FinFET,” in Proc. Device Res. Conf., 2001, pp. 24-25. [69]Y.-K. Choi, T.-H. King, and C. Hu, “Nanoscale CMOS Spacer FinFET for the Terabit Era,” IEEE Electron Device Lett., vol. 23, no. 1, January, 2002, pp. 25-27. [70]N. Lindert, L. Chang, Y.-K. Choi, E. H. Anderson, W.-C. Lee, T.-J. King, J. Bokor, and C. Hu, “Sub-60-nm Quasi-planar FinFETs fabricated using a simplified process,” IEEE Trans. Electron Devices, vol. 22, no. 10, Oct., 2001, pp. 487-489. [71]G. Pei, J. Kedzierski, P. Oldiges, M. Ieong, and E.C.-C. Kan, “FinFET design considerations based on 3-D simulation and analytical modeling,” IEEE Transactions on Electron Devices, vol. 49 , Issue: 8 , Aug., 2002, pp. 1411 – 1419. [72]S.-H. Oh, D. Monroe, and J.M. Hergenrother, “Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, sur-rounding-gate MOSFETs,” IEEE Electron Device Letters, Volume: 21 , Issue: 9 , Sept., 2000, pp. 445 – 447. [73]G. Pei, J. Kedzierski, P. Oldiges, M. Leong, and C.C. Kan,”FinFET De-sign consideration based on 3-D simulation and analytical model-ing,”IEEE Trans Electron Devices,vol.49, 2002, pp.1411-1419. [74]Y. Ma, Z. Li, L. Liu, L. Tian, and Z. Yu,”Effective density-of-states ap-proach to QM correction in MOS structure,” Solid-State Electron.,vol. 44, pp. 401-407,2000. [75]H.-S. Wong, D. J. Frank, and P. M. Solomon, “Device design considera-tion for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET’s at the 25nm channel length generation,”in IEDM Tech. Dig., 1998,pp. 407-410. [76]Int. Technol. Roadmap for Semiconductors, Semiconductor Industry Assoc., San Jose, CA, 1999. [77]Y.Taur, C.H.Wann, and D.J.Frank.”25nm COMS design considerations,” in IEDM Tech. Dig.,1998, pp.789-792. [78]Pirovano, A.; Lacaita, A.L.; Spinelli, A.S, “Two-dimensional quantum effects in nanoscale MOSFETs” IEEE Transactions on Electron Devices, vol. 49, Issue: 1 , Jan., 2002, pp. 25 -31. [79]L. Chang, S. Tang, T. J. King, J. Bokor, and C. Hu, “ Gate length scaling and threshold voltage control of double-gate MOSFET’s,” in IEDM Tech. Dig., 2000, pp. 719-722. [80]Advance MOS Device Physics. New York: Academic, 1989, vol.18. [81]J.Chen, T. Y. Chan, I. C. Chen, P.K. Ko, and C. Hu, “ Subbreaksown drain leakage current in MOSFET,” IEEE Electron Device Lett., vol. EDL-8, 1987, pp. 515-517. [82]T. Ishiyama and Y. Omua, “ Influence of superficial Si layer thickness on band-to-band tunneling current characteristics in ultra-thin n-channel metal-oxide-semiconductor field-effect-transistor by separation by im-planted oxygen (nMOSFET/SIMOX),” Jpn. J. Appl. Phys., vol. 36, 1997, pp.264-267. [83]E. Merzbacher, Quantum Mechanics, 3rd ed. New York: Wiley. [84]Nakajima, H.; Yanagi, S.; Komiya, K.; Omura, Y, “Off-leakage and drive current characteristics of sub-100-nm SOI MOSFETs and impact of quantum tunnel current” IEEE Transactions on Electron Devices, vol. 49, Issue: 10 , Oct, 2002 ,pp.: 1775 -1782.
|