臺灣博碩士論文加值系統

近年來有關環繞式閘極結構電晶體的研究陸續被提出而且備受矚目，對於未來的超大型積體電路設計這些研究展露以下環繞式閘極的優點: 有效抑制短通道效應、高封裝密度、高速截止頻率、低功率消耗、堆疊電路設計的應用、傑出的閘極控制通道能力、有效抑制邊緣電場導致通道能障下降效應，因此發展一個精確預測環繞式閘極元件特性之包含矽基體與閘極絕緣層的分析模型已是刻不容緩的事。
基於非摻雜環繞式閘極結構之矽基體和閘極絕緣層的帕森方程式之完全封閉型解，於本研究中首次將次臨界分析模型推導出來，吾人根據分離變數之疊加法與簡化二維邊界條件推導出此分析模型，此模組顯示出電位分佈、短通道臨界電壓縮減、次臨界電流、次臨界斜率、汲極偏壓導致通道能障降低效應，和因使用高閘極介電值絕緣層所造成的邊緣電場導致通道能障下降效應的解析值，此模型之演算結果與數值分析之模擬數據相當接近，並且發現非摻雜環繞式閘極結構電晶體能夠有效的抑制短通道效應與邊緣電場導致通道能障下降效應，由於此模型的計算效能所以可應用在SPICE之模擬。

In recent years, studies about Surrounding-Gate (SG) transistor have successively been proposed, and have attracted a lot of attention. For future ULSI's design, it is shown that SG transistor have the following advantages, such as: reduced short channel effects (SCEs) effectively, high packing density, high-speed cut-off frequency, low-power consumption, the application of Stacked circuit design, the excellent gate control over the channel and reduced fringe-induced barrier lowering (FIBL) effectively. To make the device be applied to the simulation, it is necessary to develop an analytical 2D model to predict precisely the performance of the SG MOSFET.
In this thesis, based on fully closed-form solutions of Poisson’s equation in both regions of Si body and gate insulator, a physical and analytical model for undoped Surrounding-Gate (SG) MOSFETs has been derived. It uses the superposition method and simplifying assumptions of 2D boundary conditions to derive the model. The model shows the distribution of electric potential, short channel threshold voltage roll-off (ΔVTH), subthreshold current, subthreshold slope (Swing), drain-induced barrier lowering (DIBL) effects and FIBL effects arising from the use of high-k gate dielectric. The new model is verified by published numerical simulations with close agreement. It is found that the SCEs and FIBL effects for undoped SG MOSFETs can be effectively reduced by using both short channel length and high-k gate dielectric. Due to its computational efficiency, this model can be applied for SPICE simulation.

Contents
摘要 i
Abstract ii
Acknowledgements iii
Contents iv
List of Table vi
List of Figures vii
Chapter 1 Introduction 1
1.1 VLSI Overview 1
1.2 Device Scaling and Problem 2
1.3 Surrounding-Gate MOSFETs Survey 5
1.4 Motive of the Thesis 9
Chapter 2 2D Threshold Voltage Model for Undoped Surrounding-Gate MOSFETs 10
2.1 Motive 10
2.2 Model Derivation 11
2.3 2D Boundary Conditions Value Problem 13
2.4 Scaling Length 16
2.5 Coefficients Solution 20
2.6 2D Generalized Potential Model 24
2.7 Minimum Channel Potential 27
2.8 Physical Threshold Voltage Roll-off Model 29
2.9 Drain-induced Barrier Lowering (DIBL) Model 36
2.10 Discussion and Conclusion 38
Chapter 3 2D Subthreshold Current Model for Surrounding-Gate MOSFETs 42
3.1 Motive 42
3.2 Subthreshold Slope Model 44
3.3 Analytic Subthreshold Current Model 47
3.4 Discussion and Conclusions 51
Chapter 4 The Model for SG MOSFETs with High-k Dielectrics 56
4.1 Motive 56
4.2 Issues of High-K material and FIBL effect 58
4.3 High-K Model 61
4.4 Discussion and Conclusion 74
Chapter 5 Conclusions and Future Works 76
5.1 Conclusions 76
5.2 Future Works 78
Publications List 79
References 80
Introduction of the Author 87

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