臺灣博碩士論文加值系統

目前超大型積體電路持續發展，而造就更小的晶片以及更小的內部元件尺寸，因此連接積體電路內部各元件的內連線也趨向於緊密複雜。由於晶片面積不斷縮小以及操作時脈頻率不斷升高，導致內連線間寄生效應及串音現象變的極為嚴重。在此論文中，吾人將對串音模組及寄生電容模組做更深入的研究與分析。
在過去大部分的串音模組都只有考慮到電容耦合效應，但是由於目前的操作頻率越來越高，電感耦合效應勢必考慮進去。在電感耦合中以互感最為主要，互感將會造成輸入雜訊脈衝到被干擾線，雜訊脈衝有可能會造成系統機能的錯誤以及改變被干擾線上的傳播延遲。吾人依據傳輸線原理推導出一各簡單的串音模組，此模組能成功地顯示出由電感耦合和電容耦合所造成的雜訊波形。
另外吾人也針對既有的寄生電容模組提出未考慮到的幾何參數，經由二維模擬軟體 ─ Raphael 所萃取出的數據資料顯示出，在非平面的相互交叉內連線結構下，導線的傾斜量也將影響到寄生電容的數值。因此為了能更完美地預測出寄生電容的數值，勢必導線的傾斜量也須考慮進去。

Continuous advancements in the field of very large scale integrated circuits and very high speed integrated circuits have resulted in smaller chip sizes, smaller device geometries, and millions of closely spaced interconnections in one or more levels that connect the various components on the chip. Due to steady decrease in chip area and increase in clock frequencies, the influence of interconnects parasitic on circuit behavior becomes significant. In this study, we focus on modeling improvement for RLC crosstalk and parasitic capacitance.
In the past, most existing noise models only consider capacitive coupling. However, at current operating frequencies, inductive crosstalk effects should be included for complete coupling noise analysis. One aspect of on-chip inductance that has not been studied well is mutual inductive coupling. Mutual inductance causes signal integrity issues by injecting noise pulses on a victim line. The injected noise can either cause functional failure or change the delay of the victim line. Based on transmission line theory, we propose a simple RLC crosstalk model. Due to its simplicity, the model is useful in understanding noise waveform shapes due to capacitive and inductive coupling and also their dependencies on various parameters. The proposed model will be particularly useful in investigating the effect of physical design changes (linewidth, spacing, etc.) on noise.
Furthermore, based on 2D simulation result, we show that magnitude of slope regarding non-planar interconnects will affect the parasitic capacitance of crossover interconnects, which is ignored by previous investigations. To precisely predict the capacitances of the 2D interconnect, the sloping issue should be accounted for.

摘要…...……………………………………………………………………………….....I
Abstract.............................................................................................................................II
Acknowledgements………………………………………………………………….....III
Chapter 1 Abstract (Chinese)........................................................................................IV
Chapter 2 Abstract (Chinese)..........................................................................................V
Chapter 3 Abstract (Chinese)........................................................................................VI
Chapter 4 Abstract (Chinese).......................................................................................VII
Chapter 5 Abstract (Chinese)........................................................................................XI
List of Figures……………………………………………………………………….....VI
Chapter 1 Introduction…………………………………………………………………..1
1.1 Interconnection’s review………………………………………………………..1
1.2 Scope and Brief Description of this Thesis……………………………………..4
Chapter 2 Raphael Overview…………………………………………………………….5
2.1 Fundamentals…………………………………………………………………...5
2.2 Interconnect Configurations…………………………………………………….7
Chapter 3 Crosstalk Noise Model for On-chip RLC Wiring…………………………….9
3.1 Motivations……………………………………………………………………..9
3.2 RLC Crosstalk Analysis……………………………………………………….10
3.3 Crosstalk Noise Model for On-chip RLC Wiring……………………………..15
3.4 Simulation and Conclusion……………………………………………………18
Chapter 4 Parasitic Capacitance Modeling……………………………………………..20
4.1 Motivations……………………………………………………………………20
4.2 Parasitic Capacitance Model reviewing……………………………………….20
4.2.1 Capacitance of each region……………………………...……………..23
4.3 Sloping Problem………………………………………………………………28
Chapter 5 Conclusions and Future Works……………………………………………...33
5.1 Conclusions……………………………………………………………………33
5.1.1 RLC Crosstalk Noise Model…………………………………………...33
5.1.2 Parasitic Capacitance Model…………………………………………...33
5.2 Future Works………………………………………………………………….34
Publications List………………………………………………………………………..35
References………………………………………………………………………………36
Introduction of Author………………………………………………………………….40

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