臺灣博碩士論文加值系統

H.264/AVC具有極佳的編碼壓縮效能，但高壓縮率的編碼技術，其對傳輸誤碼的要求更為嚴荷。為此本論文分析H.264/AVC碼流之重要性，且提出一種結合渦輪碼及用不均等錯誤保護方式來供H.264/AVC用之新型分層編解碼演算法。其中藉由渦輪碼提供不同之編碼碼率及解碼遞迴次數，對於H.264/AVC碼流中重要的部份給予比較高的錯誤保護，而不重要的部份給予比較低的錯誤保護，在本論文中提出四層不同層級，對應四種不同的錯誤保護，藉由渦輪碼具有極佳的錯誤更正能力且效能十分接近仙農極限之優點，可讓傳輸誤碼大為降低。此外在本論文中我們也分析比較未分層編碼搭配渦輪碼相等錯誤保護(EEP)與分層編碼搭配渦輪碼不均等錯誤保護(UEP)之效能。在節省頻寬架構裡，UEP1相較EEP1其頻寬可節省16.19%~19.56%，而消耗功率只增加分層編解碼之平均功率0.93mW、視訊PSNR只下降0.28db~0.39db。在節省功率架構裡，UEP2相較EEP2其消耗功率可節省約30.22%~34.02%，且視訊PSNR可提昇2.63db~2.93db，而頻寬需增加20.66%~25.72%。其中EEP1採用1/3碼率且四次遞迴，而UEP1採用1/3、1/3、1/2、1/2碼率，四、四、六、六遞迴次數，排列方式由重要性高至低，而EEP2採用1/2碼率且八次遞迴，UEP2採用1/3、1/3、1/2、1/2碼率，四、四、六、四遞迴次數，排列方式由重要性高至低。為了驗證架構的可行性，我們採用Xilinx Vertix-4 FPGA予以驗証。最後再以TSMC 0.18μm 1P6M CMOS製程來完成一個分層編碼器與分層解碼器的晶片佈局與驗證。

H.264/AVC has excellent compression performance for video code. However, the requirement of transmission error bits is stricter for high compression rate encoding technology. In this thesis, we analysis the significance of the H.264/AVC compressed bitstream and propose a new layer codec algorithm which combines UEP method with turbo code. Turbo code can provide various coding rate and iteration times, which gives higher error protection for the important parts of H.264/AVC compressed bitstream and lower error protection for the unimportant parts. In our design, we separate the H.264/AVC compressed bitstream into four different levels to provide four different error protection abilities. We also compare the performance of non-layered coding with turbo code equal error protection and layered coding with turbo code unequal error protection. Simulation results show that UEP1 with bandwidth-saving architecture can save 16.19%~19.56% bandwidth in comparisons with EEP1 and the power dissipation only increases 0.93mW, the video PSNR only decreases 0.28db~0.39db. In the power-saving architecture, UEP2 can save 30.22%~34.02% power dissipation in comparisons with EEP2 and the video PSNR increases 2.63db~2.93db, the bandwidth increases 20.66%~25.72%. For demonstrating this method, we use Xilinx Vertix-4 FPGA to test and verify the layered codec architecture. Finally, we have designed a layered encoder and layered decoder chips with TSMC 1P6M CMOS technology. These chips can operate up to 101.MHz and the chip area of layered encoder occupies 0.96 mm 0.96 mm, layered decoder occupies 1.13mm 1.13mm.

目 錄

中文摘要 i
英文摘要 ii
誌謝 iii
目錄 iv
表目錄 vi
圖目錄 viii
第一章 緒論 1
第二章 H.264/AVC 4
2.1 H.264/AVC編解碼器 5
2.1.1 H.264編碼器 5
2.1.2 H.264解碼器 6
2.2 H.264/AVC的檔次 7
2.3 H.264 擴展檔次碼流 8
2.4錯誤恢復編碼 10
2.4.1 分層編碼 11
2.4.2 MDC 13
2.4.3 獨立段預測 16
2.4.4 插入I 16
2.5不均等錯誤保護 16
2.5.1 不均等渦輪編碼碼率之錯誤保護 17
2.5.2 不均等渦輪解碼遞迴次數之錯誤保護 18
第三章 H.264之分層編碼模擬 21
3.1 H.264編碼器之設定 22
3.2 H.264解碼器之修改演算法 24
3.3分層編碼演算法 26
3.4渦輪編碼碼率對H.264影像的影響 27
3.4.1 Foreman之模擬結果 27
3.4.2 Salesman之模擬結果 28
3.4.3 Highway drive之模擬結果 30
3.4.4 News之模擬結果 31
3.4.5 模擬結果之討論 33
3.5渦輪解碼遞迴次數對H.264影像的影響 33
3.5.1 Foreman之模擬結果 33
3.5.2 Salesman之模擬結果 35
3.5.3 Highway drive之模擬結果 36
3.5.4 News之模擬結果 38
3.5.5 模擬結果之討論 39
第四章 分層編解碼與渦輪碼UEP架構設計 40
4.1分層編碼碼流之句法及語義 41
4.2分層編碼器架構設計 48
4.2.1分層編碼程序 49
4.2.2同步位元正確之分層編碼程序 51
4.3不均等錯誤保護架構設計 52
4.3.1節省頻寬設計 53
4.3.2節省功率設計 54
4.4分層解碼器架構設計 55
4.4.1分層解碼程序 55
4.4.2假設同步位元正確之分層解碼程序 56
第五章 分層編解碼器FPGA驗證 57
5.1 FPGA設計流程 57
5.2 HDL行為描述模擬 58
5.2.1分層編碼之行為描述模擬 58
5.2.2分層解碼之行為描述模擬 59
5.3後模擬 60
5.3.1分層編碼之後模擬 61
5.3.2分層解碼之後模擬 62
5.4 FPGA實際訊號擷取 64
5.4.1分層編碼之實際訊號擷取 64
5.4.2分層解碼之實際訊號擷取 65
5.5 FPGA設計資源比較 67
5.5.1分層編碼之設計資源 67
5.5.2分層解碼之設計資源 69
5.6 FPGA功率比較 71
5.6.1分層編碼之功率 71
5.6.2分層解碼之功率 71
5.6.3渦輪解碼之功率 72
5.6.4功率之比較 72
第六章 分層編解碼器晶片設計 73
6.1晶片設計流程 73
6.2晶片電路模擬 74
6.2.1分層編碼之電路模擬 74
6.2.2分層解碼之電路模擬 75
6.3晶片合成與實體佈局 76
6.3.1分層編碼之晶片合成與實體佈局 76
6.3.2分層解碼之晶片合成與實體佈局 78
第七章 結論 80
參考文獻 81
附錄
待投稿論文
『A New VLSI Architecture of H.264 Layer Codec and UEP for Turbo Code』
83

參考文獻

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