臺灣博碩士論文加值系統

渦輪碼是一種前向錯誤更正碼，利用大量的運算與多次的疊代來達到接近夏農極限的錯誤更正效能。但傳統渦輪解碼在硬體的實現上需要使用到大量的記憶體，而且解碼輸出延遲時間也比較長。為此本論文藉由分析研究渦輪演算法與滑動視窗演算法，提出一種新型免額外逆向遞迴運算延遲演算法，該一方法可以將解碼延遲由傳統四個L長度縮短成只用一個滑動視窗解碼延遲。在硬體的實現上，此一新架構僅需增加一個額外的記憶體即可省去一個逆向遞迴計算單元和二個內部暫存記憶體。相較於傳統的架構，使用本篇論文所提出的演算法，可在SISO的部份省去27%~45%的記憶體位元數，而在實際記憶體的面積上也可省去65%~68%。為了檢驗此架構的可行性，我們先使用了Xilinx FPGA HW-V4-ML402-USA加以驗證，最後我們也將此一架構以TSMC 0.18 μm 1P6M製程實際完成一顆低延遲渦輪解碼晶片設計，實驗顯示此一解碼器時脈為104.1MHz，整個電路含I/O PAD的面積是1.9 mm 1.9 mm，可供未來無線通訊IP之應用。

Turbo code is a forward error correct code which has good error correction capability and near Shannon limiting performance. Traditional turbo decoder needs large memory size and has long decoding latency for implementation. This paper presents a dummy-beta-latency-free algorithm which can reduce the decoding latency of sliding window from 4L to 1L. In hardware implementation, we can use a dummy-beta memory unit to replace one backward calculation unit and two SISO sub-memories. Experimental results show that our architecture can save 27%~45% memory bit and 65%~68% memory area. Then, we have verified this algorithm using Xilinx FPGA (HW-V4-ML402-USA) system. Finally, a dummy-beta-latency-free turbo decoder is designed using TSMC 0.18μm 1P6M CMOS technology. The chip occupies 1.9mm 1.9mm and has a clock frequency of 104.1Mbps.

中文摘要 i
英文摘要 ii
誌謝 iii
目錄 iv
表目錄 vi
圖目錄 vii
第一章 緒論 1
1.1 研究動機 1
1.2 渦輪碼簡介 2
1.3 論文章節排列 3
第二章 渦輪碼 4
2.1 渦輪編碼器 5
2.2 遞迴解碼演算法 6
2.3 最佳化與次佳化演算法 8
2.3.1 MAP 演算法 9
2.3.2 Max-Log-MAP 演算法 14
2.3.3 Log-MAP Algorithm 16
2.3.4 SW-Log-MAP Algorithm 18
第三章 免額外逆向遞迴運算延遲演算法 21
3.1 免額外逆向遞迴運算延遲演算法 21
3.2 改良型免額外逆向遞迴運算延遲演算法 26
3.3 DBLF演算法對於錯誤更正效能的影響 29
3.4 DBM位元數的影響 31
第四章 改良型免額外逆向遞迴運算延遲渦輪解碼電路架構設計 34
4.1 傳統渦輪解碼器架構 35
4.2 改良型DBLF的SISO解碼器設計 36
4.2.1 記憶體存取電路 40
4.2.2 路徑計量值計算單元(BMC) 43
4.2.3 正向(逆向)遞迴計算單元(Alpha、Beta) 44
4.2.5 對數相似度計算單元 47
第五章 改良型免額外逆向遞迴運算延遲渦輪解碼FPGA驗證 49
5.1 FPGA設計流程 49
5.2 Verilog程式碼行為描述模擬波形 51
5.3 Verilog程式碼合成後模擬波形 53
5.4 FPGA實際訊號擷取 54
5.4 FPGA設計資源比較 56
第六章 改良型免額外逆向遞迴運算延遲渦輪解碼晶片設計 57
6.1 晶片設計流程 57
6.2 晶片電路模擬 58
6.3 晶片合成與實體佈局 60
6.4 記憶體比較 62
第七章 結論 63
參考文獻 64
附錄
投稿論文
“ A Dummy-Beta Latency Free VLSI Architecture for MAP Decoder,” in Proc. of The 2006 Symposium of Photonic Devices and System Application, pp. 86-87, April 1-4. 2006. 67
待投稿論文
“ A Dummy-Beta Latency Free VLSI Architecture for MAP Decoder,” 70

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