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研究生:蔡寶鳴
研究生(外文):Bao-Ming Tsai
論文名稱:場發射顯示器系統整合與模組設計
論文名稱(外文):SYSTEM INTEGRATION AND MODULE DESIGN OF FIELD EMISSION DISPLAY
指導教授:施文欽
指導教授(外文):Wen-Ching Shih
學位類別:碩士
校院名稱:大同大學
系所名稱:光電工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:英文
論文頁數:61
中文關鍵詞:場發射顯示器數位控制電路
外文關鍵詞:Digital control circuitField emission display
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場發射顯示器具有視角廣,尺寸大,厚度薄,響應速度快,高對比等優點,在各種顯示器當中,是非常有潛力的產品。本論文會針對五點七吋場發射顯示器的面板製程與數位邏輯控制系統做深入的分析探討。此數位系統主要功能為將畫面資料經過處理之後,配合場發射顯示器的顯示原理將畫面顯示在螢幕上。我們將會先介紹數位邏輯系統周邊的輸出入資料格式及使用元件的規格,再進一步用模擬的結果印證之。最後,加上量測並完成場發射顯示器模組。
Field Emission Display (FED) is a potential product. It has advantages over other display panels by wide viewing angle, large size, thinness, fast response, and high contrast ratio. In this thesis, the panel fabrication and the digital logic control system of 5.7-inch FED is analyzed in detail. The main function of this digital system is to display image data on the panel by the processed system. In this thesis, input and output data format of the digital logic system and specifications of components are introduced first. Then the simulation results are shown to verify the design. At last, we added the measurement to complete field emission display module.
ACKNOWLEDGEMENT i
ABSTRACT (English) ii
ABSTRACT (Chinese) iii
CONTENTS iv
LIST OF FIGURES vi
CHAPTER 1 INTRODUCTION 1
1.1 Background 1
1.2 Development of FED 2
1.3 Overview of the thesis 3
CHAPTER 2 INTRODUCTION OF FIELD EMISSION DISPLAY 4
2.1 The characteristics of field emission display 4
2.2 Field emission theory (Folwer-Nordheim theory) 4
2.3 Basic FED structure 9
2.4 Lighting principle of field emission display 12
CHAPTER 3 STRUCTURE OF FIELD EMISSION DISPLAY MODULE 17
3.1 Module of FED 17
3.2 DVI board 18
3.3 Memory 19
3.3.1 Specification and configuration of SRAM 20
3.3.2 Specification and configuration of SDRAM 20
3.4 Drive IC 22
3.4.1 Scan driver 22
3.4.2 Data driver 24
CHAPTER 4 DIGITAL CONTROL SYSTEM OF FIELD EMISSION DISPLAY 27
4.1 Design of FPGA 27
4.2 Design of Scaler 28
4.3 Input block 29
4.3.1 Input buffer controller 32
4.4 SRAM design 35
4.5 SDRAM design 36
4.5.1 SDRAM initial 38
4.5.2 SDRAM write 39
4.5.3 SDRAM read 41
4.5.4 SDRAM mode register 42
4.6 Output block 43
4.6.1 Output buffer controller 46
4.7 Timing controller 48
4.7.1 Scan driver 49
4.7.2 Data driver 49
CHAPTER 5 SIMULATION RESULTS OF DIGITAL CONTROL SYSTEM 51
5.1 Functional simulation of scaler 51
5.2 Functional simulation of SRAM 52
5.2.1 Write function of SRAM 53
5.2.2 Read function of SRAM 54
5.3 Functional simulation of SDRAM 55
5.3.1 Write function of SDRAM 56
5.3.2 Read function of SDRAM 57
5.4 Timing simulation of driver control signal 58
CHAPTER 6 SUMMARY 60
6.1 Conclusion 60
6.2 Future Work 60
REFERENCES 62
[1] Funaki Y, Mochizuki Y, Flat panel display market to reach 10 trillion yen by 2010. Nikkei Microdevices, Flat panel display yearbook, InterLingua, Redondo Beach, California, USA, p.75, 1999.
[2] LETI: R. Meyer, “Recent development on microtips display at LETI,” IVMC’91 Technical Digest, p. 6, 1991.
[3] Guey-Ren Su, "Application and Characterization of Nitrogen Incorporated Diamond Like Carbon Films on Field Emission Array", TTIT, Master thesis, 1998.
[4] Mitsuru Tanaka, Yuji Obara, “Development of a 11.3-inch VGA Full-Color FED”, SID 04 DIGEST, p.832, 2004.
[5]S. Newman, R. Smith, C.Penn, “Development of a 5.1 inch Field Emission Display”, Society for Information Display, May 1998.
[6]T. Oguchi, “A 36-inch Surface-conduction Electron-emitter Display”, SID 05 DIGEST, p.1929, 2005.
[7] S.M. Sze, Physics of Semiconductor Devices. New York: Wiley, 1981.
[8] R. H. Fowler and L. W. Nordheim, “Electron emission in intense field,” Proc. R. SOC. A229, p. 173, 1928.
[9] Silicon Image data sheet, CP1160/CP1161 Starter Kit User’s Guide.
[10] IDT data sheet, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) ,IDT71V416S.
[11] Micron data sheet, SYNCHRONOUS DRAM, MT48LC4M32B2 - 1 MEG x 32 x 4 BANKS.
[12] ST data sheet, Scan Driver for Plasma Display Panels, STV7697B.
[13] NEC data sheet, MOS INTEGRATED CIRCUIT, μPD16347.
[14] NEC data sheet, MOS Integrated Circuit, “ μ PD4516421A,4516821A, 4516161A for Rev. P, 16M-bit Synchronous DRAM”, April 1998.
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