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研究生:吳泰頡
研究生(外文):Tai-Jie Wu
論文名稱:合成SystemC到同步與非同步混合電路
論文名稱(外文):Synthesizing SystemC into Mixed-design Circuits
指導教授:鄭福炯鄭福炯引用關係
指導教授(外文):Fu-Chiung Cheng
學位類別:碩士
校院名稱:大同大學
系所名稱:資訊工程學系(所)
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:英文
論文頁數:65
中文關鍵詞:非同步電路合成
外文關鍵詞:asynchronousSystemC
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隨著高頻通訊時代的來臨,全球各國紛紛提高對電磁干擾與電磁相容性的要求。在電子產品設計中,可以用接地、電磁屏蔽、濾波三種方式來降低電磁干擾及完成電磁相容設計。但最根本的解決方式則是減少電磁輻射產生的機率。高頻率clock的運作是電子系統中產生電磁輻射的主要來源,採用非同步電路設計能夠有效的減少電磁輻射產生的途徑。本研究主旨在於將System描述合成為同步與非同步混合設計電路。透過將SystemC軟體描述部分轉換成非同步電路與原本硬體同步電路部份進行結合。包含同步電路、非同步電路及同步到非同步的溝通介面,藉由此架構來達成低耗電極低電磁干擾電路的實作。
Because the age of high frequency communication comes, every country over the world increases the demand for electro-magnetic interference (EMI) and electro-magnetic compatibility (EMC). Ground connection, electromagnetic screen and filter can be used to reduce EMI and to achieve the design of EMC in electronic products. But the fundamental way is to decrease the generating of electro-magnetic radiation. The high frequency clock generation is the major source of electro-magnetic radiation in electronic products and this can be avoided by exploiting asynchronous circuits to decrease electro-magnetic radiation generation. The purpose of this thesis is to propose a methodology to automatically synthesize SystemC description to mixed-design circuits containing synchronous circuit, asynchronous circuit and their interface for low power and low EMI design.
ABSTRACT
摘要
TABLE OF CONTENTS
LIST OF FIGURES
CHAPTER 1 INTRODUCTION
CHAPTER 2 BACKGROUND
2.1 SystemC
2.1.1 SystemC Language Architecture
2.1.2 Simulation with SystemC
2.1.3 Implementation and Synthesis
2.2 Java Compiler Compiler
2.3 Extended Activity Diagram
2.3.1 Basic Components of Extended Activity Diagram
2.3.2 Basic Structure of Extended Activity Diagram
CHAPTER 3 PREVIOUS WORKS
3.1 SOCAD
3.1.1 SOCAD Design Flow
3.1.2 Java to Extended Activity Diagram Translation
3.1.3 Extended Activity Diagram to Hardware Component Graph Translation
3.1.4 Hardware Component Graph to VHDL Translation
3.1.5 Optimization
3.1.6 Summary
3.2 Decompose Loop Structure
3.2.1 Methodology of Loop Decompose
3.2.2 Summary
CHAPTER 4 DESIGN AND IMPLEMENTATION
4.1 Synthesis Flow
4.2 SystemC to Extended Activity Diagram Translation
4.2.1 Parser Generation
4.2.2 Translation Algorithm
4.2.3 Examples
4.3 Asynchronous EAD Translation Flow
4.4 Synchronous EAD Translation Flow
4.4.1 Translation with Direct Mapping
4.4.2 Translation with Finite State Machine
4.5 Mixed-design Interface
4.5.1 Synchronous to Asynchronous (S2A) Interface
4.5.2 Synchronous to Asynchronous Interface with Stoppable Clock
CHAPTER 5 EXAMPLES
CHAPTER 6 CONCLUSIONS AND FUTURE WORKS
6.1 Conclusions
6.2 Future Works
BIBLIOGRAPHY
[1]Kees van Berkel, Joep Kessels, Marly Roncken, and Frits Schalij, "The VLSI-programming language Tangram and its translation into handshake circuits," presented at Design Automation, European, 1991.
[2]The Balsa Asynchronous Synthesis System. 2006. The University of Manchester. May 28, 2006 http://www.cs.manchester.ac.uk/apt/projects/tools/balsa/
[3]Open SystemC Initiative. 2006. Open SystemC Initiative. May 28, 2006 http://www.systemc.org/
[4]Stuart Swan, Cadence Design Systems, Inc. “SystemC v2.0.1 White Paper”. May 2001.
[5]Preeti Ranjan Panda, "SystemC - a modeling platform supporting multiple design abstractions," presented at System Synthesis, The 14th International Symposium, 2001.
[6]Synopsys. “CoCentricTM SystemC Compiler RTL User and Modeling Guide”. August 2001.
[7]Synopsys. “CoCentricTM SystemC Compiler Behavioral User Guide”. March 2001
[8]Synopsys. “CoCentricTM SystemC Compiler Behavioral Modeling Guide”. March 2001.
[9]Compilers, translation between SystemC and VHDL/Verilog. 2006. Prosilog. May 28, 2006 http://www.prosilog.com/products/compilers/products_compilers.html
[10]SystemCrafter SC. 2006. SystemCrafter. May 28, 2006 http://www.systemcrafter.com/
[11]Chih-Chiang Nine, "Compiling Java programs into Modified Activity Diagrams," Tatung, 2003.
[12]Shu-Ming Chang, "Compiling Activity Diagram into Self-Timed Systems in VHDL," Tatung, 2003.
[13]Java Compiler Compiler. 2006. java.net. May 28, 2006 https://javacc.dev.java.net/
[14]Christian Cote and Zeljko Zilic, "Automated SystemC to VHDL Translation in Hardware/Software Codesign," presented at Electronics, Circuits and Systems, 9th IEEE International Conference, 2002.
[15]Karlsruhe SystemC Parser Suite.2006. FZI. May 28, 2006 http://www.fzi.de/sim/kascpar.html
[16]Ming-Hsiu Chiang, "Design and implementation of optimization algorithms in a cad tool for system-on-chip design," Tatung, 2003.
[17]Peter L. Flake and Simon J. Davidmann, "Superlog, a unified design language for system-on-chip," presented at Design Automation Conference, Asia and South Pacific, 2000.
[18]Kuan-Wei Lin, "A CAD Tool for System-On-a-Chip Design Based on Self-timed Technology," Tatung, 2001.
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