臺灣博碩士論文加值系統

個人行動通訊服務的未來趨勢勢必將牽扯大量的數據資料傳輸。影像串流、即時影像電話以及其他所有與影像有關的服務均是下一世代行動通訊服務的重點。再者，如何有效結合既有的無線區域網路技術、充分利用固定網路上的資源，亦是次世代行動通訊系統的設計重點之ㄧ。這明確地指出系統設計上的重要條件：多重標準可能性及更大的訊號傳輸頻寬。
本篇論文提出並分析了一適合 GSM/WCDMA/WIFI 三重標準之中頻數位轉換器。一個另類的，結合低雜訊、串接式結構的架構，被用以實現此三重標準之中頻數位轉換器。此中頻數位轉換器的原型晶片將以 TSMC 0.35 CMOS 2P4M 製程技術製作。

Future trend of personal mobile communication services are going to be involved with large amount of data information. Video streams, Real-time Video Phone and all the other video concerned services should be achievable for the next generation cellular system. Moreover, the accessibility to the WLAN (Wireless Local Area Network) is a must for advanced personal information services. All the demands lead to a clear system requirement: Multi-mode ability and Wide transceiving bandwidth.
In the thesis, a multi-mode of GSM/WCDMA/WIFI IF digitizer is proposed and analyzed. An alternative low-distortion cascaded bandpass delta-sigma modulator is proposed and used to construct the multi-mode IF digitizer. The prototype chip is designed and implemented in TSMC 0.35 CMOS process with 3.3V power supply.

ENGLISH ABSTRACT i
CHINESE ABSTRACT ii
ACKNOWLEDGEMENT iii
TABLE OF CONTENTS iv
LIST OF FIGURES vii
CHAPTER
I. INTRODUCTION 1
1.1 Beyond the 3G Cellular System 1
1.2 Motivations and Research Goal 2
1.3 Thesis Outline 2
II. IF DIGITIZATION 3
2.1 Superheterodyne Receiver 3
2.2 Direct-Conversion Receiver 4
2.3 Low-IF Receiver 4
2.4 Digital-IF Receiver 5
III. DELTA-SIGMA MODULATION 6
3.1 Analog-to-Digital Conversion 6
3.1.1 Sampling 6
3.1.2 Quantization 7
3.1.3 Oversampling 12
3.2 Delta-Sigma Modulation 13
3.2.1 First-order Noise Shaping 15
3.2.2 Second-order Noise Shaping 16
3.2.3 Multi-Stage Noise Shaping 18
3.2.4 Lowpass-to-Bandpass Transformation 20
IV. THE DESIGN OF A GSM/WCDMA/WIFI TRI-STANDARD IF-DIGITIZER 21
4.1 Low-distortion Topology 21
4.2 Wideband Multi-Stage Noise Shaping 23
4.2.1 Topology 24
4.3 A W-MASH 4-4 wideband IF Digitizer 24
4.4 Modeling of the Resonators 28
4.4.1 Double Delay Resonator 28
4.4.2 Tunable Resonator 34
4.5 System-Level Simulation with MATLAB 36
4.5.1 Optimized Loop Gain Coefficients 36
V. PROTOTYPE CHIP IMPLEMENTATION 48
5.1 Switch Level Design 48
5.2 Design of the Operational Amplifier 51
5.2.1 Gain-Boosting 54
5.2.2 Common-Mode Feedback 54
5.3 Design of the Switch 56
5.3.1 Charge Injection 57
5.4 Implementation of Three-Bit Quantizers 58
5.5 Uneven Clock Phases problem 61
5.5.1 Skew-Insensitive Clock Generator 62
5.6 Prototype and SPICE Simulation Results 64
VI. CONCLUSIONS 68
REFERENCES 69

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