臺灣博碩士論文加值系統

具有低頻寬、高解析度等優點的超取樣和差調變技術之數位/類比轉換器，已被廣泛使用於音響系統上。本篇論文主要設計與實現一個應用於數位音頻之和差數位類比轉換器。此系統具有16/18/20/24位元資料輸入格式、44.1kHz/88.2kHz/48kHz/ 96kHz/192kHz輸入取樣頻率規格，此外所用的和差調變器有3/5階，以及128/256兩種超取樣倍率可供選擇。
系統架構是由三個串聯的升頻內插器與一個3/5階和差調變器所組成。第一級與第二級的內插器為Half-band低通濾波器，第三級的內插器為sinc2濾波器；和差調變器屬於CIFB架構，並設計將3階架構與5階架構中相同部份予以共用，以減少硬體使用資源。
在系統設計上，首先我們使用MATLAB進行系統層級之架構模擬，以求出相關參數值，並確定系統穩定性與效能，以加速整個設計流程。接下來，使用VHDL描述電路架構及以Xilinx ISE6.3完成電路合成；為了有效測試電路，我們設計一個測試機制，利用ModelSim6.0模擬並驗證設計電路之功能與效能。
最後使用Xilinx Virtex-Ⅱ與Spartan3 FPGA進行實際硬體測試。測試結果如下：128倍超取樣之3階和差調變器的訊號雜訊比為92.7dB@-6dBFS，128倍超取樣之5階和差調變器的訊號雜訊比為123.5dB@-6dBFS。

Oversampling and sigma-delta modulation techniques have advantages in low bandwidth and high resolution, and have already been used to implement the digital to analog converter (DAC) in the audio system extensively. In this thesis, a sigma-delta DAC suitable for digital audio system has been designed. This circuit provides multiple data input formats (16/18/20/24-bit), multiple input sample rates (44.1kHz/ 88.2kHz/48kHz/96kHz/192kHz) and two different oversampling ratios (128/256). In addition, the order of the modulator can be chosen to be either 3 or 5.
The system is composed of 3 stages of upsampling digital interpolation filters and a 3rd/5th-order sigma-delta modulator (SDM). The first and second stages of the interpolators are designed as half-band low pass filters, and the third stage is designed as a sinc2 filter. The sigma-delta modulator is based on the Cascade of Integrators Feedback form (CIFB) architecture, and the 3rd- and 5th-order SDMs are designed such that they can share some parts to reduce hardware resources.
First, MATLAB is used to get the result of system-level simulation and to obtain parameters suitable for hardware implementation. VHDL is used to describe the circuit, and Xilinx ISE6.3 is used for synthesis. The simulation is performed using ModelSim6.0 with a testbench to verify the circuit function and performance, and then the code is downloaded to Xilinx FPGA Virtex-Ⅱand Spartan3 to test the system and to verify the theoretical prediction. Finally, two experimental results are given. For the one with 24bit, 128x oversampling 3rd-order SDM, the signal to noise ratio (SNR) is 92.7dB @ -6dBFS. The other with 24bit, 128x oversampling 5th-order SDM has an SNR of 123.5dB @ -6dBFS.

ABSTRACT I
摘要 II
誌謝 III
CONTENTS IV
LIST OF FIGURES VI
LIST OF TABLES XIII
CHAPTER 1 INTRODUCTION 1
1.1 Background 1
1.2 Motivation 2
1.3 Organization of This Thesis 2
CHAPTER 2 FUNDAMENTALS OF SIGMA-DELTA MODULATOR 4
2.1 Quantization 4
2.2 Nyquist Rate Conversion 5
2.3 Oversampling Conversion 6
2.4 Noise Shaping 9
2.4.1 First-order Sigma-Delta Modulator 10
2.4.2 Second-order Sigma-Delta Modulator 11
CHAPTER 3 SYSTEM DESIGN AND MATLAB SIMULATION 13
3.1 System Design and Implementation Flow 14
3.1.1 Software Simulation and Verification 15
3.1.2 Hardware Test and Verification 15
3.2 Interpolator Design and Simulation 15
3.2.1 Half-Band Filter1 Design and Simulation 18
3.2.2 Half-Band Filter2 Design and Simulation 23
3.2.3 Sinc2 Filter Design and Simulation 28
3.2.4 Simulink Simulation 34
3.3 Sigma-Delta Modulator Design and Simulation 38
3.3.1 3rd-order Sigma-Delta Modulator Design and Simulation 39
3.3.2 5th-order Sigma-Delta Modulator Design and Simulation 43
3.3.3 3rd/5th-order Sigma-Delta Modulator Pre-VHDL Architecture Simulation 47
3.4 System Simulation 53
3.5 Two-Tone System Simulation 56
CHAPTER 4 SYSTEM DESIGN IN VHDL 58
4.1 FPGA Design Flow 58
4.2 System Modules 59
4.3 Clock_Module 61
4.4 Multi-Input Data Format Design 65
4.5 HBF1 Module 67
4.6 HBF2 Module 68
4.7 Sinc2 Module 71
4.8 SDM Module 72
4.9 System Simulation 76
CHAPTER 5 FPGA IMPLEMENTATION AND EXPERIMENTAL RESULTS 80
5.1 FPGA Implementation 80
5.2 Download FPGA 84
5.3 Experimental Results 86
CHAPTER 6 CONCLUSIONS 92
6.1 Conclusions 92
6.2 Future Work 92
REFERENCES 93

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