臺灣博碩士論文加值系統

隨著科秓的日新月進，愈來愈多的電子設備及產品走向無線通訊的境界，而在 1999 年由 IEEE 協會制定出 802.11 的規格後，各大小廠商莫不盡力的將此一規格實現及改進，除了創造出無限的商機外，也為廣大的使用者帶來了莫大的方便。
在本論文中將針對 802.11 的規格裏所提到的 Media Access Control(MAC) 部份作討論及研究，並且根據 802.11b 所制定的規格參數，使用 VHSIC Hardware Description Language(VHDL) 設計一個符合 802.11 MAC 的接收部份模組，其中包含了同步處理、重組訊框處理等，最後利用 Xilinx 公司的可程式化邏輯陣列 (Field Programmable Gate Array, FPGA) Virtex II XC2V1000 平台將此設計作實現，在此設計中的處理速度可逹 72 MHz。

There are many new technologies are updated everyday, more and more electric equipments and products move towards the realm of the wireless communication. After the IEEE associations define 802.11 specifications in 1997, all kind of the manufacturer do the best to realize and improve this specification, besides creating the limitless business opportunity, also brought greatest convenience for everyone.
In this thesis, we will focus on 802.11 MAC section in receiver part, which includes MAC functions, frame formats, and some important parts, include synchronization problem and DeFragmentation frame function.
Finally we use VHDL (VHSIC Hardware Description Language) to design a MAC receiver part depend on 802.11b parameters, then implement on Xilinx FPGA (Field Programmable Gate Array, FPGA) Virtex II XC2V1000 platform and verified all functions by logic analyzer.

摘要 I
ABSTRACT II
ACKNOWLEDGEMENT III
TABLES OF CONTENTS IV
LIST OF FIGURES VIII
LIST OF TABLES XI
CHAPTER 1 INTRODUCTION 1
1.1 Introduction 1
1.2 Motivation 1
1.3 Organization of this thesis 2
CHAPTER 2 802.11 MAC ARCHITECTURE 3
2.1 Introduction to IEEE 802.11 3
2.2 802.11 Network Topology 4
2.2.1 Basic Service Set (BSS) 4
2.2.1.1 Independent BSS (IBSS) 5
2.2.1.2 Infrastructure BSS 6
2.2.2 Distribution System (DS) 6
2.2.3 Extend Service Set (ESS) 7
2.3 802.11 MAC Operation 8
2.3.1 Distributed Coordination Function (DCF) 8
2.3.1.1 CSMA/CA Mechanism 9
2.3.1.2 Interframe Space (IFS) 9
2.3.1.3 RTS/CTS 11
2.3.1.4 Back-off mechanism 12
2.3.2 Point Coordination Function (PCF) 13
2.4 802.11 MAC Frame Formats 14
2.4.1 Frame Control Field 14
2.4.2 Duration/ID Field 18
2.4.3 Address Field 19
2.4.3.1 BSSID Field 19
2.4.3.2 Destination Address (DA) Field 19
2.4.3.3 Source Address (SA) Field 19
2.4.3.4 Receiver Address (RA) Field 20
2.4.3.5 Transmitter Address (TA) Field 20
2.4.4 Sequence Control Field 20
2.4.4.1 Fragment Number Field 21
2.4.4.2 Sequence Number Field 21
2.4.5 Frame Body Field 21
2.4.6 Frame Check Sequence (FCS) Field 22
2.5 Individual Control Frame Formats 22
2.5.1 Request To Send (RTS) Frame 22
2.5.2 Clear To Send (CTS) Frame 23
2.5.3 Acknowledge (ACK) Frame 23
2.6 Fragmentation and Reassembly 24
2.7 Synchronization 25
2.7.1 Synchronization in an Infrastructure BSS 25
2.7.2 Synchronization in an IBSS 25
2.7.3 Passive Scan 26
2.7.4 Active Scan 26
CHAPTER 3 IMPLEMENTATION 29
3.1 System Architecture 29
3.2 Receiver Module Specification 29
3.3 TIMER Module 31
3.4 Synchronization Module 33
3.5 CRC32 Module 34
3.6 DeFragmentation Module 36
3.7 Functional Verify Procedure 38
CHAPTER 4 SIMULATION AND VERIFY RESULTS 40
4.1 Design Environment 40
4.2 Design flow 40
4.3 Design status 41
4.4 Simulation and Results 41
4.4.1 CRC32 function 43
4.4.2 Synchronization function 44
4.4.3 Defragmentation function 45
4.4.4 Full function verification 49
4.5 Hardware verification 49
CHAPTER 5 CONCLUSIONS 54
REFERENCES 56

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