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研究生:李隆仁
研究生(外文):Lung-Jen Lee
論文名稱:充分利用電路中必要之反閘改善連線延遲
論文名稱(外文):Using Essential Inverters for Interconnect Delay Reduction
指導教授:林榮彬林榮彬引用關係
學位類別:碩士
校院名稱:元智大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:英文
論文頁數:40
中文關鍵詞:反閘連線延遲緩衝器
外文關鍵詞:inverterinterconnect delaybuffer
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隨著電晶體製造技術不斷創新,影響整體電路性能表現之主要因素已逐漸轉為電路中的連線延遲大小。這個問題的有效解決方案之一便是在適當位置”置入緩衝器” 。然而,增加緩衝器雖然有助於減少電路連線延遲,但同樣的也增加了整體電路使用的面積大小、功率消耗並增加電路壅塞程度。本研究目的在探討如何充分利用必要之反閘在電路中的推力來改善電路連線延遲的問題並有效減少緩衝器的使用量。必要的反閘乃在能使電路產生正確功能。刪除任何一個反閘將會導致電路的錯誤。大部分的必要反閘屬於同向閘,如AND,OR等。
以較大型電路如ITC99’而言,本研究所提方法相較於未利用必要反閘的方法,在時效性上有0.78%至4.90%的改進幅度,而對於較小型電路如ISCAS89’則無明顯改善。
With the advance of VLSI process technology, interconnect delay increasely dominates the circuit performance. Buffer insertion is one of the crucial approaches to this problem. However, buffer insertion not only increases total chip area but also increases power dissipation. In this thesis, we propose to use essential inverters to reduce the use of buffers. An essential inverter is an inverter required to make a circuit function correctly. Removing of any essential inverters will result in malfunctioning of a circuit. Most of the essential inverters are embedded in positive unate gates such as AND, OR etc. In our experiment, we extract essential inverters from positive unate gates.
Compared to without using essential inverters, our approach results in 0.78% to 4.90% timing improvement on ITC99’ benchmark circuits with larger sizes while no improvement on ISCAS89’ benchmark suits with smaller sizes.
書名頁……………………………………………………………………i
摘要……………………………………………………………………ii
Abstract………………………………………………………………iii
誌謝……………………………………………………………………iv
Table of Contents ……………………………………………………v
List of Tables………………………………………………………vi
List of Figures……………………………………………………viii
Chapter 1. Introduction……………………………………………1
1.1 Background and Motivation…………………………………1
1.2 Related Work……………………………………………………3
1.3 Thesis Organization…………………………………………6
Chapter 2. Methodology………………………………………………7
2.1 Using traditional design flow……………………………9
2.2 Set-don’t-use in standard cell library………………11
2.3 Gate replacing method………………………………………13
2.3.1 With Driving Strength Replaced Ratio 1:M………13
2.3.2 With Driving Strength Replaced Ratio 2:M………15
2.3.3 With Driving Strength Replaced Ratio M:M………17
Chapter 3. Experiment………………………………………………19
3.1 Experimental Setup…………………………………………19
3.2 Experimental Results………………………………………24
3.3 Experimental Results Analyses…………………………30
Chapter 4. Conclusions and Future work………………………37
4.1 Contribution…………………………………………………37
4.2 Future Work……………………………………………………38
References……………………………………………………………39
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S. T. Quay1, S. S. Sapatnekar4, A. J. Sullivan1, P. Villarrubia1,Buffered Steiner Trees for Difficult Instances.ISPD’01, April 1-4, 2001
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