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研究生:許淳凱
研究生(外文):Chun-Kai Hsu
論文名稱:減少擷取時間產生的能量消耗之隨意位元填法
論文名稱(外文):Don’t Care Bits Filling for Reducing Capture Power
指導教授:曾王道
學位類別:碩士
校院名稱:元智大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:英文
論文頁數:24
中文關鍵詞:能量
外文關鍵詞:reducingreductioncapturepower
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在超大型積體電路的設計和測試中,功率的消耗已經成為一個重要的議題。對於以掃描為基礎的測試架構(scan based testing architecture)來說,功率消耗也是一個嚴重的問題。因為在此架構下測試電路,會使得許多邏輯閘同時動作而造成瞬間大量的能量消耗。在擷取測試結果的時脈(capture cycle)中,過多的能量消耗將會造成電源電壓降(IR drop)而干擾測試結果,進而造成可觀的良率損失。本篇論文中,我們提出一種方法可以降低在擷取測試結果時所造成的能量耗損。在測試向量(test vector)中的隨意位元(don’t care bit)的邏輯值為何並不會對錯誤偵測率(fault coverage)造成影響,因此我們可以利用這些隨意位元來減少擷取時所產生的功率消耗。簡單來說,我們把測試向量和測試結果中,對應位置上的隨意位元填上相同的值,如此便能夠減少在擷取結果時,對應位置上的位元值所發生的衝突,換句話說,就是減少邏輯閘由零變一或由一變零的情形。由於指定隨意位元邏輯值的順序將影響減少能量的多少,因此我們利用轉變密度評估方程式(induced activity function)來決定這些隨意位元的考慮順序。我們所提出的方法不會對硬體造成任何的負擔,也不會對電路的效能有所影響。
Power dissipation has become an important issue in VLSI design and testing. Scan based testing architecture suffers from power dissipation problem very much because a number of gates may switch at the same time while testing. Excessive power dissipation during capture cycle will cause IR drop and corrupt the test response of the circuit which result in significant yield loss. This thesis proposes a method to reduce the power dissipation during capture cycle. The don’t care bits in a test vector are those that can change their values to opposite values and will not effect the fault coverage. These don’t care bits are used in our method for reducing power dissipation during capture cycle. We can assign the same value to the corresponding bit pair of test vector and test response to avoid transition occurring during capture cycle. Induced activity function is introduced for selecting which bit pair should be processed first. This method needs not any extra hardware supporting, therefore there are no area overhead and performance loss in the proposed approach.
書名頁...i
中文摘要...ii
英文摘要...iii
誌謝...iv
Contents...v
List of Figures...vi
List of Tables...vii
Chapter 1. Introduction...1
Chapter 2. Related Work...5
Chapter 3. Background...8
3.1 Induced Activity Function...8
3.2 Line Justification...11
Chapter 4. Proposed Method...13
Chapter 5. Experimental Results...20
Chapter 6. Conclusions...22
Reference...23
[1]P.M. Rosinger, B.M. Al-Hashimi, and N. Nicolici, “Scan Architecture for Shift and Capture Cycle Power Reduction,” In Proc. International Symposium on Defect and Fault Tolerance in VLSI System, 2002, pp. 129-137.

[2]Kuen-Jong Lee, Shaing-Jer Hsu and Chia-Ming Ho, “Test Power Reduction with Multiple Capture Orders,” Test Symposium, 2004 13th Asian 15-17 Nov. 2004 Page(s):26 – 31.

[3]Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang,
Kewal K. Saluja, and Kozo Kinoshita, “On Low-Capture-Power Test Generation for Scan Testing,” VLSI Test Symposium, 2005. Proceedings. 23rd IEEE
1-5 May 2005 Page(s):265 – 270.

[4]K. Miyase and S. Kajihara, “XID: Don''t Care Identification of Test Patterns for Combinational Circuits,” IEEE Trans. Computer-Aided Design, Vol. 23, No. 2, pp. 321-326, Feb. 2004.

[5]Kajihara, S.; Ishida, K.; Miyase, K.;"Test vector modification for power reduction during scan testing," VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE 28 April-2 May 2002 Page(s):160 - 165.

[6]Sinanoglu, O.; Orailoglu, A.;"Test data manipulation techniques for energy-frugal, rapid scan test ," Test Symposium, 2003. ATS 2003. 12th Asian 16-19 Nov. 2003 Page(s):202 - 207.

[7]Girard, P.; Guiller, L.; Landrault, C.; Pravossoudovitch, S.;"A test vector ordering technique for switching activity reduction during test operation ," VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on 4-6 March 1999 Page(s):24 - 27.

[8]Bellos, M.; Bakalis, D.; Nikolos, D.;"Scan cell ordering for low power BIST
," VLSI, 2004. Proceedings. IEEE Computer society Annual Symposium on 19-20 Feb. 2004 Page(s):281 - 284.

[9]Sinanoglu, O.; Orailoglu, A.;"Aggressive test power reduction through test stimuli transformation ," Computer Design, 2003. Proceedings. 21st International Conference on 13-15 Oct. 2003 Page(s):542 - 547.

[10]Il-soo Lee; Yong Min Hur; Ambler, T.;"The efficient multiple scan chain architecture reducing power dissipation and test time," Test Symposium, 2004. 13th Asian 15-17 Nov. 2004 Page(s):94 - 97.

[11]Sankaralingam, R., and N.A. Touba, "Reducing Power Dissipation During Test Using Scan Chain Disable", Proc. of VLSI Test Symposium, pp. 319-324, 2000.

[12]Dong Hyun Baik; Saluja, K.K.; Kajihara, S.;"Random access scan: a solution to test power, test data volume and test time,"VLSI Design, 2004. Proceedings. 17th International Conference on 2004 Page(s):883 - 888.

[13]Sankaralingam, R.; Oruganti, R.R.; Touba, N.A.;"Static compaction techniques to control scan vector power dissipation," VLSI Test Symposium, 2000. Proceedings. 18th IEEE 30 April-4 May 2000 Page(s):35 - 40.

[14]P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, “A Test Vector Ordering Technique for Switching Activity Reduction during Test Operation”, in Proc. 9th Great Lakes Symp. VLSI, Mar. 1999, pp.24-27.

[15]Sankaralingam, R.; Touba, N.A.;"Controlling peak power during scan testing
," VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE 28 April-2 May 2002 Page(s):153 - 159.
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