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研究生:蔡佳青
研究生(外文):Chia-Ching Tsai
論文名稱:基礎於測試向量重新排序之方法改良以降低電路測試期間之功率消耗
論文名稱(外文):Power Reduction for Circuit Under Testing Based on Test Vector Reordering
指導教授:曾王道
學位類別:碩士
校院名稱:元智大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:英文
論文頁數:22
中文關鍵詞:測試向量重新排序
外文關鍵詞:Test Vector Reordering
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由於科技發展迅速,超大型積體電路的設計發展與製造技術在最近幾年中成長更為快速,擁有高效能與高密度整合電路的研發是業界相同目標,相對的使得晶片整體複雜度增加。因此,測試時間與功率消耗的增減,將影響整個生產成本。在本論文中,我們將針對整合電路(Combination Circuit)在測試時的功率消耗問題,提出一個優化的改良技術。整個論文的技術核心在於減少整合電路內部信號(signal)的轉換次數(Transition Count),以達到降低功率消耗的目的。而此技術的主要觀念是利用任意兩組輸入測試向量(Test Vector)之間,每一個相關信號位元前後的差異轉換次數,進而重新編排輸入測試向量的順序來達成研究的目標。我們提出四個步驟來解決這些問題。首先考慮整合電路內部各邏輯閘的轉換機率,表示每個輸入信號對內部造成影響的程度;緊接著分別計算所有相關測試向量間,主要輸入與掃描輸入兩部分的差異轉換次數,由上述兩個步驟我們可獲得各組測試向量間的總轉換次數並賦予不同的權重值(weight),依此建構一個有向圖,並使用貪婪演算法求取最適的測試向量編排順序。綜合上述,我們選取標準的受測整合電路來進行驗證,並將測試向量組中未考慮到掃描輸入部分的相關論文建立實驗對照組,由最後的實驗結果得知,將比對照實驗組有效降低電路內部轉換次數。因此,本論文提出的方法將有效降低整合電路的消耗功率。
As the development in science and technology is fast, the design and manufacturing technology of the Very Large-Scale Integrated circuit (VLSI) is developed and grown up faster during recent years. It is the same goal of industry to achieve the research and development of the high performance and density of combination circuit. Ironically, the chip is getting more complex. Therefore, the amount of test time and power consumption will influence the whole production cost. In this thesis, we will put forward an optimized technology for improvement of power consumption of Combination Circuit while testing. The main technology of this thesis is decreasing the number of internal signal transition counts so as to reduce the power consumption. And the main idea of this technology is using the difference of number of conversion of every relevant signal location of two inputs Test Vector wantonly, and then rearranges the vector order to reach the goal studied. We propose four steps to solve this problem. First of all, we shall consider the probability of transfer of internal gates of combination circuit. It indicates the internal influence of each input signal. Then, calculates the difference of number of conversion of main and scan input. Following the two steps, we can get the total transfer counts of each group of vectors under test and give it different weight. Base on this to construct a vector figure, and then using greedy algorithm to secure the optimized arrangement of test vectors. Conclusively, we select standard combination circuit to verify this technology. So, the method that this thesis puts forward will reduce effectively the power consumption of the combination circuit.
中文摘要 i
英文摘要 ii
誌 謝 iv
Contents v
List of Figures vii
List of Tables viii
Chapter 1. Introduction 1
Chapter 2. Preliminaries 3
Chapter 3. Literature Review 6
3.1 Hamming distance and Hamiltonian path 7
3.2 Induced activity function 8
Chapter 4. Proposed method 12
4.1 Induced activity function calculation 12
4.2 Transition count calculation 13
4.3 Directed graph construction 16
4.4 Test vector ordering 16
Chapter 5. Experimental Results 18
5.1 Experimental environment 18
5.2 Experimental results 18
Chapter 6. Conclusions 20
Reference 21
[1] Kaushik Roy, Rabindra K.Roy and Abhijit Chatterjee, “Stress Testing of Combinational VLSI Circuits Using Existing Test Set”, VLSI Technology, Systems, and Applications, June 1995,pp.93-98.

[2] P. Girard, C. Landrault, S. Pravossoudovitch and D.Severac , “Reducing Power Consumption during Test Application by Test Vector Ordering”, Proceedings of the IEEE International Symposium, Circuits and Systems ,1998,pp.296-299.

[3] P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, “A Test Vector Ordering Technique for Switching Activity Reduction during Test Operation”, Proc. 9th Great Lakes Symp. VLSI, Mar. 1999, pp.24-27.

[4] X.Kavousianos, D.Bakalis, M.Bellos and D. Nikolos, “An Efficient Test Vector Ordering Method for Low Power Testing”, Proceedings. IEEE Computer society Annual Symposium,2004,pp.285-288.

[5] Y. Bonhomme, P. Girard, C. Landrault, and S. Pravossoudovitch, “Power Driven Chaining of Flip-flops in Scan Architectures”, Proc. of Int’l Test Conf., 2002, pp. 796-802.

[6] Y. Bonhomme, P. Girard,L.Guiller, C. Landrault, and S. Pravossoudovitch, “Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint”, Test Conference, Proceedings. ITC,2003,pp.488-493.

[7] R.Sankaralingam, R. Oruganti, and N.A. Touba, “Static Compaction Techniques to Control Scan Vector power Dissipation”, Proc. 18th VLSI Test Symp., IEEE CS Press, Los Alamitos, Calif., 2000, pp.35-42.

[8] Vinary Dabholkar, Sreejit Chakravarty, “Techniques for Minimizing Power Dissipation in Scan and Combinational Circuits During Test Application”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions,1998,pp.1325-1333.

[9] S. Wang and S. K. Gupta, “DS-LFSR: A BIST TPG for Low Switching Activity”, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, July 2002, pp.842-851.

[10] O. Sinanoglu, I. Bayraktaroglu, and A. Orailoglu, “Scan Power Reduction Through Test Data Transition Frequency Analysis”, Proc of the Int’l Test conf., 2002, pp.844-850.

[11] M. Bells, D. Bakalis and D. Nikolos, “Scan Cell Ordering for Low Power BIST”, Proc. IEEE Computer Society Annual Symposium, Feb. 2004, pp.281-284.

[12] Hamzaoglu, I.; Patel, J.H., “Test set compaction algorithms for combinational circuits”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Volume 19, Issue 8, 2000, pp957 – 963

[13] Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, and A. Virazel, “Design of Routing-Constrained Low Power Scan Chains”, Proc. of the Design, Automation and Test in Europe Conference and Exhibition, 2004, pp. 62-67.
[14] P. Girard, “Survey of Low –Power Testing of VLSI Circuits”, IEEE Design & Test of Computer, Vol.19, May-June 2002, pp.82-92.

[15]Ozgur Sinanoglu,Ismet Bayraktroglu and Alex Orailoglu, “Scan Power Reduction Through Test Data Transition Frequency Analysis” , Test Conference, Proceedings. International, 2002 , pp.844-850.

[16]Ranganathan Sankaralingam and Nur A.Touba, “Controlling Peak Power During Scan Testing”,VLSI Test Symposium, Proceedings 20th IEEE, May 2002, pp.153-159.
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