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研究生:曾國恩
研究生(外文):Kuo-En Tseng
論文名稱:應用多重掃描鏈以及字典壓縮法減少測試資料
論文名稱(外文):Dictionary based Data Compression for SOC with Multiple Scan Chains
指導教授:曾王道
學位類別:碩士
校院名稱:元智大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:中文
論文頁數:20
中文關鍵詞:slicesscan chaindictionary-based
外文關鍵詞:橫切組掃描鏈字典
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  • 被引用被引用:0
  • 點閱點閱:125
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在SOC的設計中,減少測試時間和測試資料是一個主要的挑戰。在此,我們提出了一個應用在多重掃描鏈設計上的字典資料壓縮法。為了減少由自動測試環境 (ATE)傳送到受測電路(CUT))的資料量,我們將要送到掃描鏈 (scan chain)的橫切組 (slices)分成常使用和不常使用兩類。將常使用的存放在字典的前端而不常使用的存放在字典的尾端,我們將使用兩種不同常度的索引(index)來代表兩種類型的slices。當要使用到低位址的資料,只需要用很短的index就可以找到我們要的資料,因此資料量就可以被減少。而這方法跟變動長度的加密法 (variable encoding)相比在受測電路上只要用很簡單的解壓縮邏輯(decompression logic)就能夠達到很高的壓縮率。進一步,使用重新排序掃描細胞 (scan cell reorder)的方法可以再次的提升壓縮率。使用字典 (dictionary-based)可以用很少的ATE通道 (channel)就能驅動大量的scan chain,這是一個非常適合低價位的測試,在實驗結果可以知道這個方法對於測試時間跟測試資料量都有相當大的縮減。
Reducing test application time and test data volume are major challenges in SoC design. In this thesis we propose a new dictionary-based test data encoding technique for multiscan-based designs. To reduce the data volume transferred from ATE to the core under test, we classify the data slices of the scan chain into high using frequency and low using frequency. The high using frequency slices are arranged in the low address portion of the dictionary and the low using frequency slices are arranged in the high address portion. Two different lengths of indices are then assigned for these two classes of slices to point to the entries of the dictionary. When sending a high using frequency of slice, only low portion of address is needed and the data volume can then be reduced. The decompression logic in the core under test is very simply and we can get high compression ratio by using variable encoding technique without increasing the complexity of decompression logic. Furthermore, to reduce the size of the dictionary, we use a scan cell reorder method to increase the compression ratio. Dictionary-based is based on the use of a small number of ATE channels to deliver compressed test patterns from the tester to the chip and to drive a large number of internal scan chains in the circuit under test and it is especially suitable for a reduced pin-count and low-cost DFT test environment. Experimental results show the proposed approach indeed can get a high compression ratio of the test data and can as well reduce the test times.
Abstract …………………………………………………………………………..iv
Contents …………………………………………………………………………..vii
List of Figures .......…………………………………………………………..viii
List of Tables ……………………………………………………………………..ix
Chapter 1. Introduction ……………………………………………………..1
Chapter 2. Related Work ……………………………………………………..3
Chapter 3. Proposed method …………………………………………………4
3.1 Compression Scheme ……………………………………………..5
3.2 Advance Compress Ratio ……………………………………………11
3.3 Compression Ratio ………………………………………………..…13
Chapter 4. Experimental Results …………………………………………..…14
Chapter 5. Conclusion ……………………………………………………..…18
References ……………………………………………………………………..…19
[1] S. Reda and A. Orailoglu, “Reducing test application time through test data mutation encoding”, Proc. Design, Automation and Test in Europe Conf., pp. 387-393, 2002.

[2] I. Bayraktaroglu and A. Orailoglu, “Test volume and application time reduction through scan chain concealment”, Proc. ACM/IEEE Design Automation Conf., pp. 151–155, 2001.
[3] A. El-Maleh, S. al Zahir, and E. Khan, “A geometric-primitives-based compression scheme for testing systems-on-chip”, Proc. VLSITest Symp., pp. 54–59, 2001.

[4] Jas, A., Ghosh-Dastidar, J., and Touba, N.A., “Scan Vector Compressiofiecompression using Statistical Coding,” Proc. IEEE VLSl Test Symposium, pp.114-120, 1999.

[5]Jas, A., Ghosh-Dastidar, J., Ng, M.-E. and Touba, N.A., “An Efficient Test Vector Compression Scheme Using Selective Huffman Coding,” IEEE Trans. on CAD, vol. 22, No. 6, pp.797-806, June 2003.

[6]Chandra, A., and Chakrabarty, K., “System-on-a-chip test data compression and decompression architectures based on Golomb codes”, IEEE Trans. Computer-Aided Design, vol. 20, pp. 355-368, March2001.

[7]Chandra, A., and Chakrabarty, K., “Test Data Compression and TestResource Partitioning for System-on-a-Chip Using Frequency-Directed Run-Length (FDR) Codes,” IEEE Trans. on Computers (TCOMP), pp.

[8] Chandra, A., and Chakrabarty, K., “A Unified Approach to ReduceSOC Test Data Volume, Scan Power and Testing Time,” IEEE Trans. On Computer-Aided Design (TCAD), pp. 352-363.2003.

[9] El-Maleh, A., and AI-Abaji, R., “Extended Frequency-Directed Run- Length Codes with Improved Application to System-on-a-Chip Test Data Compression,” Proc. Int. Conf. Electronics, Circuits and Systems, pp. 439-452.2002.

[l0] Rosinger, P., Gonciari, P., AI-Hashimi, B., and Nicolici, N., “Simultaneous Reduction in Volume of Test Data and Power Dissipation for System-on-a-Chip,” Electronics Letters, vol. 37, no. 24.

[11]Gonciari, P. T., AI-Hashimi, B. and Nicolici, N., “Improving compression ratio, area overhead, and test application time for systemon- a-chip test data compression/decompression,” Proc. of Design, Automation and Test in Europe Conf., pp. 604-61 I , 2002.

[12] Reddy, S. M., Miyase. K., Kajihara. S., and Pomeranz. I., “On test data volume reduction for multiple scan chain design”, Proc. VLSl Test Symp., pp. 103-108,2002.
[13] A. Jas, J. Ghosh-Dastidar and N. A. Touba, “Scan vector compression/ decompression using statistical coding,” Proc. VLSIT est Symp., pp. 114-120, 1999.

[14] H. Vranken, T.Waayers, H. Fleury and D. Lelouvier, “Enhanced reduced pin-count test for full-scan designs”, Proc. Int. Test Conf., pp. 738–747, 2001.
[15]S. M. Reddy, K. Miyase, S. Kajihara, and I. Pomeranz, “On test data volume reduction for multiple scan chain design”, Proc. VLSITest Symp., pp. 103–108, 2002.

[16]Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa and Tatsuo Ohtsuki ” Reducing Test Data Volume for Multiscan-based Designs through Single/Sequence Mixed Encoding”
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