臺灣博碩士論文加值系統

在電路佈局設計中，鑽孔(via)用來連接上下相鄰兩層金屬的導線。隨著電晶體製程的縮小，製程變異可能會使鑽孔製造失敗，鑽孔失敗會增加電路的電阻，導致時序問題，甚或使訊號斷路而造成電路功能錯誤，這些都嚴重地影響晶片的良率(yield)。最常用來改善此問題的方法即在每個鑽孔旁邊加上一個作為備份用的鑽孔(redundant-via)。商業用軟體工具及近來的研究在這方面有很好成就，但是我們發現，第一層鑽孔(via 1)(連接第一層金屬及第二層金屬)的備份嵌入個數會受限於標準元件本身，因為標準元件並不是特別為了備份鑽孔而設計。位於最下層的第一層鑽孔製造失敗的機率最高，因此備份的第一層鑽孔對於提高良率來說最為重要。
在這篇論文中我們提出一個設計標準元件的方法來促進第一層備份鑽孔的嵌入，我們設計兩個版本的元件庫DV1及DV2，DV1版本的元件提供每個輸入/輸出腳位足夠打兩個鑽孔的第一層金屬面積，DV2版本的元件我們在每個輸入/輸出腳位上打兩個鑽孔，這樣可以保證繞線前有百分之百的第一層備份鑽孔。我們也建立一個結合DV1及DV2的元件庫DMix。和商業用元件庫所得到的結果比較，DV1最多可減少6%的落單鑽孔數(周圍沒有備份鑽孔的鑽孔)及1%的第一層落單鑽孔數，此外可減少1%~3%的總鑽孔數。DV2可減少67%~83%的落單鑽孔數及95%~97%的第一層落單鑽孔數，但在總鑽孔數上會增加10%~16%。綜合的DMix可減少46%~60%的落單鑽孔數及54%~69%的第一層落單鑽孔數，在總鑽孔數上最多只增加6%。我們在(幾乎)沒有增加多餘的元件面積及繞線長度下得到上述的結果。

In the layout design, a via connects two or more wire segments of different metal layers. With device and interconnect width keep shrinking, process variation may cause via failure in manufacturing. A failed via can increase the resistance of a net and cause timing problems or even result in an open net and thus leads to false functionality. These will seriously impact design yield. A well known solution to yield loss due to via failure is to add a redundant via adjacent to each single via. Commercial tools and some recent work have done a great job in redundant via insertion. However, they are found with limited capability of inserting more vias (called via1) between metal 1 and metal 2. Such a limitation is caused by the way the standard cells are designed since they are not designed for serving redundant-via insertion. The probability of via1 failure is higher hence redundant via1 is critical for improving the chip yield.
In this thesis we proposed a standard cell design methodology to facilitate via1s insertion. We design two cell libraries DV1 and DV2. DV1 provides each pin with sufficient metal 1 area for holding two vias. DV2 pre-installs two via1s directly at each pin. The via1 duplication is guaranteed before routing. We also form a third library called DMix by combining DV1 and DV2 together. Compared to the results obtained using a commercial cell library, DV1 achieves up to 6% reduction in widowed vias (a via not accompanied by a redundant via) , up to 1% reduction in widowed via1s, and 1%~3% reduction in total via count. DV2 achieves 67%~83% reduction in widowed vias and 95%~97% reduction in widowed via1s, but at the expense of 10%~16% increase in total via count. Library DMix can achieve 46%~60% reduction in widowed vias and 54%~69% reduction in widowed via1s at the expense of at most 6% increase in total via count. We achieve the above results (almost) at no extra cost in total cell area and wire length.

書名頁 i
論文口試委員審定書 ii
授權書 iii
摘要 iv
Abstract vi
誌謝 viii
Contents ix
List of Tables x
List of Figures xi
Chapter 1. Introduction 1
1.1. Background and Motivation 1
1.2. Scope of the Work 4
1.3. Thesis Organization 5
Chapter 2. Related Work 6
2.1. Routing Stage Redundant Via Insertion 6
2.2. Post-Routing Redundant Via Insertion 6
Chapter 3. Methodologies 8
3.1. Standard Cells Design 8
3.2. Cell-Based Design Flow 12
Chapter 4. Experimental Results 15
Chapter 5. Conclusion 19
References 20

[1] G. Xu, Li-Da Huang, D. Z. Pan and M. D. F. Wang, “Redundant-Via Enhanced Maze Routing for Yield Improvement”, Proc. of ASPDAC, 2005.
[2] Chien-Fu Wang, “Post-Layout Multiple Vias Insertion”, Master Thesis, Graduate Institute of Computer Engineering and Science, Yuan Ze University, July 2004
[3] K. Y. Lee and T. C. Wang, “Post-Routing Redundant Via Insertion for Yield/Reliability Improvement”, Proc. of ASPDAC, 2006, pp.303-308.
[4] H. Yao, Y. Cai, X. Hong and Q. Zhou, “Improved Multilevel Routing with Redundant Via Placement for Yield and Reliability”, Proc. of GLSVLSI, 2005.
[5] G. A. Allan, “Targeted Layout Modifications for Semiconductor Yield/Reliability Enhancement”, IEEE Trans on Semiconductor Manufacturing, vol. 17, Nov. 2004.
[6] F. Luo, Y Jia, W. W.-M. Dai, “Yield-Preferred Via Insertion Based on Novel Geotopological Technology”, Proc. of ASPDAC, 2006, pp.730-735.
[7] NanoRoute, Cadence Design Systems, Inc.
[8] UMC 0.18μm L180 Process 1.8-Volt Sage-XTM Standard Cell Library Databook, Artisan Components, Inc., Nov. 2003.