臺灣博碩士論文加值系統

本論文主要為金氧半場效電晶體BSIM4直流與射頻模型參數與大必v電晶體之研究。第一部份是利用TSMC 0.35 μm CMOS製程，設計製作符合BSIM4金氧半場效電晶體直流模型萃取程序之測試元件，共計有8組符合0.35 μm CMOS製程尺寸限制之直流測試元件作為量測之用，以得到0.35 μm CMOS製程之合理化的直流模型特性。再配合萃取軟體，可得出該製程之BSIM4直流模型參數。第二部份設計單指狀與多指狀之高頻電晶體元件，作為射頻參數萃取之用途。利用前一部份所得之直流模型，再配合高頻參數如S參數與小訊號增益之量測與萃取，再利用去嵌入化之技巧，得到TSMC 0.35 μm CMOS製程之高頻模型特性。第三部份則為CMOS必v電晶體之設計。共計製作四組尺寸不同之CMOS必v電晶體。並配合負載推移系統，量測其輸出必v、輸出輸入匹配點、放大效率，與必v增益，作為設計射頻必v放大器之參考依據。

A research of CMOS BSIM4 DC and RF model parameters and power MOS transistor is investigated in this thesis. In the first part, a set of DC test devices which is fabricated by using TSMC 0.35 μm CMOS technology is designed for the BSIM4 CMOS DC model parameters extraction. It employs eight designs in the test set for measurement that all of the devices are implemented based on the design rule of TSMC 0.35 μm CMOS technology to obtain the reasonable BSIM4 DC model parameters. By the aid of extraction software ICCAP-2006A, the DC model parameters of 0.35 μm CMOS technology were extracted. A single-finger and multi-finger high-frequency devices are used to extract the RF model parameters in the second part. The DC model parameters in the first part will be also included to derive the RF model parameters. Some of calibration kits for de-embedded are used to verify the measured S-parameters and small-signal characteristic. Following the two steps, the BSIM4 RF model parameters will be obtained. The last part is a design of CMOS power cell. There are four devices with different sizes being built up of which are measured by a load-pull system for the output power, efficiency , power gain and the optimal impedance for load and source terminals.

Acknowledgement..............................................................................................i
Abstract (in Chinese).........................................................................................ii
Abstract (in English)..........................................................................................iii
Contents............................................................................................................v
Figure Captions...............................................................................................vii
Table Captions..................................................................................................xi



u 1 Introduction 1
1.1 Development and Research...................................................................1
1.2 Motivation...............................................................................................1
1.3 Overview of this work..............................................................................3


u 2 Test Devices & BSIM4 DC Model Parameter 6
2.1 0.35 um CMOS Process.........................................................................6
2.2 Design of DC test-key.............................................................................7
2.3 Design of RF test-key..............................................................................9
2.4 BSIM4 DC Model Parameters...............................................................12
2.4.1 Threshold Voltage Model................................................................12
2.4.2 Direct Tunneling Gate Current Model.............................................17
2.4.3 Drain Current Model.......................................................................23
2.5 BSIM4 DC Model Extraction Flow and Result.......................................33


u 3 BSIM4 MOSFET RF Model Parameter 53
3.1 Introduction of BSIM4 RF Model...........................................................53
3.2 Two Port S-parameters.........................................................................54
3.3 De-embedding Method and Design of RF Model Test Devices.............55
3.4 BSIM4 RF Model Parameters...............................................................58
3.4.1 Gate Electrode and Intrinsic-Input Resistance (IIR) Model.............58
3.4.2 Substrate Resistance Network.......................................................60
3.4.3 Experimental Results of RF Device................................................61


u 4 Load-Pull System and CMOS Power cell 76
4.1 Motivation.............................................................................................76
4.2 Load-Pull System..................................................................................77
4.3 CMOS Power Cell Design.....................................................................79
4.4 Experimental Results of CMOS Power Cell..........................................80


u 5 Conclusion 96


u 6 References 99

[1]D. Su and W. McFarland, “A 2.5 V, 1-W monolithic CMOS RF power amplifier” in Proc. Custom Integrated Circuits Conf., May 1997, pp.189–192.
[2]K.C. Tsai and Gray, P.R., “A 1.9-GHz, 1-W CMOS class-E power amplifier for wireless communications” Solid-State Circuits, IEEE Journal of Volume 34, Issue 7, July 1999 Page(s):962 – 970
[3]K. Mertens and M. Steyaert, “A 700-MHz 1-W fully differential CMOS class-E power amplifier”, Solid-State Circuits, IEEE Journal of Volume 37, Issue 2, Feb. 2002 Page(s):137 – 141
[4]Changsik Yoo and Qiuting Huang, “A common-gate switched 0.9-W class-E power amplifier with 41% PAE in 0.25-μm CMOS”, Solid-State Circuits, IEEE Journal of Volume 36, Issue 5, May 2001 Page(s):823 – 830
[5]BSIM4.5.0 MOSFET Model-User''s Manual, Department of Electrical Engineering and Computer Science, University of California, Berkeley, 2004
[6]Agilent 85190A IC-CAP 2006 User''s Guide, Agilent technologies
[7]Y. C. King, H. Fujioka, S. Kamohara, K. Chen, and Chenming Hu, “DC electrical oxide thickness model for quantization of the inversion layer in MOSFETs”, Semicond. Sci. Technol., vol. 13, pp. 963-966, 1998.
[8]Weidong Liu, Xiaodong Jin, Yachin King, and Chenming Hu, “An efficient and accurate compact model for thin-oxide-MOSFET intrinsic capacitance considering the finite charge layer thickness”, IEEE Trans. Electron Devices, vol. ED-46, May, 1999
[9]Kanyu M. Cao, Weidong Liu, Xiaodong Jin, Karthik Vasanth, Keith Green, John Krick, Tom Vrotsos, and Chenming Hu,, “Modeling of pocket implanted MOSFETs for anomalous analog behavior”, Tech.Dig. of IEDM , pp. 171-174, 1999
[10]Z.H. Liu, C. Hu, J.H. Huang, T.Y. Chan, M.C. Jeng, P.K. Ko, and Y.C. Cheng, “Threshold Voltage Model For Deep-Submicron meter MOSFETs”, IEEE Tran. Electron Devices, vol. 40, pp. 86-95, 1993.
[11]J.A. Greenfield and R.W. Dutton, “Non-planar VLSI Device Analysis Using the Solution of Poisson''s Equation”, IEEE Trans. Electron Devices, vol. ED-27, p.1520, 1980.
[12]T. Y. Chen, J. Chen, P. K. Ko, C. Hu, “The impact of gate-induced drain leakage current on MOSFET scaling”, Tech. Digest of IEDM, pp. 718-721, 1987.
[13]S. A. Parke, E. Moon, H-J. Wenn, P. K. Ko, and C. Hu, “Design for suppression of gate-induced drain leakage in LDD MOSFETs using a quasi 2D analytical model”, IEEE Trans. Electron Devices, vol. 39, no. 7, pp 1694-1703, 1992.
[14]M.V. Dunga, C.H. Lin, Jane Xi, D. Lu, M. Niknejad, andC.Hu, “Modeling Advanced FET Technology in a Compact Model”, Electron Devices, IEEE Transactions on Volume 53, Issue 9, Sept. 2006 Page(s):1971 – 1978
[15]Y. Cheng, M. Jeng; Z. Liu, J. Huang, M. Chan; K. Chen, P.K. Ko, C. Hu, “A physical and scalable I-V model in BSIM3v3 for analog/digital circuit simulation” Electron Devices, IEEE Transactions on Volume 44, Issue 2, Feb. 1997 Page(s):277 – 287
[16]Xiaodong Jin, J-J Ou, C-H Chen, Weidong Liu, Paul Gray, and Chenming Hu, “An effective gate resistance model for CMOS RF and noise modeling”, Tech. Dig. of IEDM, pp. 961-964, 1998.
[17]Chao-Chih Hsiao, Ching-Wei Kuo and Yi-Jen Chan, A modified BSIM 0.35 μm MOSFET RF large-signal model for microwave circuit application”, Microwave Conference, 2000 Asia-Pacific 3-6 Dec. 2000 Page(s):1109 – 1112
[18]Joe Civello, “Addressing the challenges of RF device modeling for successful high-frequency design”, Microwave Engineering Europe ● December/January 2004 ● www.mwee.com
[19]C. Enz, and Y. Cheng, “MOS transistor modeling for RF IC design”, Solid-State Circuits, IEEE Journal of Volume 35, Issue 2, Feb. 2000 Page(s):186 – 201
[20]Yuhua Cheng, M.J. Deen, Chih-Hung Chen, “MOSFET modeling for RF IC design”, Electron Devices, IEEE Transactions on Volume 52, Issue 7, July 2005 Page(s):1286 – 1303
[21]Yuhua Cheng, M. Matloubian, “On the high-frequency characteristics of substrate resistance in RF MOSFETs”, Electron Device Letters, IEEE Volume 21, Issue 12, Dec. 2000 Page(s):604 – 606
[22]C. Enz, “An MOS transistor model for RF IC design valid in all regions of operation”, Microwave Theory and Techniques, IEEE Transactions on Volume 50, Issue 1, Part 2, Jan. 2002 Page(s):342 – 359.
[23]Yuhua Cheng; M. Matloubian, “Parameter extraction of accurate and scaleable substrate resistance components in RF MOSFETs”, Electron Device Letters, IEEE Volume 23, Issue 4, April 2002 Page(s):221 – 223
[24]Yuhua Cheng, M.J. Deen, Chih-Hung Chen, “MOSFET modeling for RF IC design” Electron Devices, IEEE Transactions on Volume 52, Issue 7, July 2005 Page(s):1286 – 1303.
[25]徐書彥 "金氧半場效電晶模型-BSIM4模型化技術與特性量測之研究" 逢甲大學電子工程系碩士論文 民國九十四年
[26]Thomas Gneiting, “BSIM4, BSIM3v3 and BSIMSOI RF MOS Modeling”, Agilent EEsof EDA Seminar April 04, 2001 Mountain View, CA, USA.
[27]“DC Characteristic of Semiconductor Power Devices”, Agilent Technology
[28]W. Liu, “MOSFET Models for SPICE Simulation, including BSIM3v3 and BSIM4” Wiley- Interscience, 2001
[29]“HP 4155A:　Semiconductor Parameter Analyzer User’s Guide: Measurement and Analysis” Agilent Technology, Oct 1998.
[30]Trond Ytterdal, Yuhua Cheng, Tor A. Fjeldly, “Device Modeling for Analog and RF CMOS Circuit Design”, Wiley- Interscience, 2003
[31]"Layout Rules for GHz Probing", Application Note Cascade Microtech
[32]林建勳 “矽鍺異質接面電晶體之高頻雜訊與必v特性之研究及其5.2GHz 射頻放大器之設計”, 國立成奶j學微電子工程研究所博士論文, 民國九十五年
[33]狶茤M “負載拉移(Load-Pull)原理於設計射頻必v放大器之應用”, 國家晶片系統設計中心
[34]Y. Takayama: “A new load-pull characterization method for microwave power transistors”, NEC Research & Development, No. 50, pp. 23-29(July 1978) also in 1976 IEEE MTT-S Int. Microwave Symp., Digest, Tech. Paper. 218-220(1976)
[35]John Sevic, “Basic Verification of Power Load－pull Systems”, MAURY MICROWAVE 1 oct, 2004
[36]“THEORY OF LOAD AND SOURCE PULL MEASUREMENT”, MAURY MICROWAVE 27 July, 1999
[37]David M. Pozar “Microwave Engineering”，John Wiley & Sons，1998
[38]Guillermo Gonzalez, “Microwave Transistor Amplifiers Analysis and Design” second edition, Prentice Hall, Upper Saddle River, New Jersey 1984.
[39]C.-H.; Su, Y.-K.; Juang, Y.-Z.; Chiu, C.-F.; Chang, S.-J.; Chen, J. F.; Tu, C.-H.;” The Optimized Geometry of the SiGe HBT Power Cell for 802.11a WLAN Applications”, Microwave and Wireless Components Letters, IEEE Volume 17, Issue 1, Jan. 2007 Page(s):49 - 51