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研究生:陳志昇
研究生(外文):Chih-sheng Chen
論文名稱:3.5-GHzCMOS壓控振盪器與分數型頻率合成器晶片設計
論文名稱(外文):Design of 3.5-GHz CMOS Voltage-Controlled Oscillator and Fractional-N Frequency Synthesizer
指導教授:張盛富
指導教授(外文):Sheng-fuh Chang
學位類別:碩士
校院名稱:國立中正大學
系所名稱:電機工程所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:中文
論文頁數:97
中文關鍵詞:壓控振盪器頻率合成器相位雜訊
外文關鍵詞:phase noisefractional-NsynthesizerVCO
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本論文研製3至4 GHz CMOS之壓控振盪器和分數型頻率合成器。首先,3-GHz壓控振盪器採用交互耦合式架構,並使用電容性源極退化技術增加頻寬,晶片可調頻率範圍為2334-2939 MHz,相位雜訊為-72 dBc/Hz@100 kHz,-114 dBc/Hz@1 MHz。第二,3.5-GHz四相位壓控振盪器採用電容基體耦合四相位,可減少採用耦合電晶體產生的雜訊及必v消耗,晶片可調頻率範圍為3187-3903 MHz,相位雜訊為-98 dBc/Hz@100 kHz,-124 dBc/Hz@1 MHz。最後,3.5-GH分數型頻率合成器包含壓控振盪器、多模數除頻器、ΣΔ調變器、相位頻率偵測器、電荷幫浦電路以及三階晶片外接迴路濾波器,扣除壓控振盪器總必v消耗27 mW,輸出頻率從3200-3784 MHz,輸出必v為-19- -15 dBm,鎖定時間約20 ms。
3-4 GHz 0.18 μm CMOS voltage-controlled oscillators and fraction-N frequency synthesizer investigated in the thesis. First, a 3-GHz cross-coupling voltage-controlled oscillator (VCO) is designed, and using capacitive source degeneration to increases frequency range. The VCO has the measured tuning range of 2334-2939 MHz, the phase noise of -72 dBc/Hz@100 kHz offset and -114 dBc/Hz@1 MHz offset. The second CMOS VCO is a 3.5-GHz quadrature VCO, and using capacitive body coupling to reduce the power dissipation and remove the additional noise contribution. The VCO has the measured tuning range of 3187-3903 MHz, the phase noise of -98 dBc/Hz@100 kHz offset and -124 dBc/Hz@1 MHz offset. A 3.5-GHz ΣΔ fractional-N frequency synthesizer is designed, including VCO, multi-modulus divider, ΣΔ modulator, phase-frequency detector, charge pump and off chip loop filter. The measurement result shows that the channel in the range of 3200-3784 MHz can be looked with 20 ms settling time, and the output power is -19 to -15 dBm with the power consumption of 27 mW.
第一章 緒論 1
1.1 研究背景 1
1.2 壓控振盪器簡介 2
1.3 頻率合成器簡介 2
1.4 研究目的及論文綱要 5
第二章 運用電容性源極退化之3-GHz壓控振盪器設計 7
2.1 電路架構分析 7
2.2 電路設計與模擬 10
2.3 量測結果與討論 16
第三章 採用基極耦合之3.5-GHz四相位壓控振盪器設計 21
3.1 電路架構分析 21
3.2 電路設計與模擬 23
3.3 量測結果與討論 26
第四章 頻率合成器原理 31
4.1 系統參數 31
4.1.1 可調頻寬 31
4.1.2 相位雜訊 31
4.1.3 鎖定時間 33
4.1.4 突波 34
4.1.5 頻率解析度 34
4.2 頻率合成器之分析 35
4.2.1 模型建立 35
4.2.2 整數型頻率合成器 38
4.2.3 分數型頻率合成器 39
4.3 採用ΣΔ調變作多除數控制之分數型頻率合成器 41
第五章 3.5-GHz分數型頻率合成器設計 50
5.1 架構分析 50
5.2 子電路設計 50
5.2.1 相位頻率偵測器 50
5.2.2 電荷幫浦 56
5.2.3 壓控振盪器 56
5.2.4 多除數除頻器 63
5.2.5 ΣΔ調變器 67
5.2.6 迴路濾波器 72
5.3 整體電路模擬與佈局 74
5.4 量測結果與討論 76
5.4.1 壓控振盪器量測結果 76
5.4.2 頻率合成器量測結果 77
第六章 結論 81
參考文獻 83
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