臺灣博碩士論文加值系統

本論文主要針對Ultra-Wide Band低頻段(3.1~5 GHz)射頻收發機CMOS晶片進行研究與製作，其中包含寬頻主動分相器、低雜訊放大器整合主動分相器及升頻混波器，晶片製作皆採用的TSMC 0.18μm 1P6M製程，量測上均採用Bond Wire將晶片整合於PCB版上。
3.1~5 GHz寬頻主動分相器，使用一顆NMOS與一顆PMOS Cascode起來，使用電流再利用技術，以節省必v消耗，量測結果顯示在頻段內，增益差在2 dB以內，相位差在10度以內，輸入輸出返回損耗均在-10dB以下，線性度上，IP1dB為-3~-3.5 dBm，IIP3為10.6~11.4 dBm，Noise Figure為9.9~13 dB。
3.1~5 GHz寬頻低雜訊放大器(Low Noise Amplifier,LNA)整合主動分相器，寬頻LNA部分採用使用兩極疊接共射級放大器與單端多閘極結構，並整合如前所述之主動分相器如前面所述，量測結果顯示在頻段內，增益差在1.2 dB以內，相位差在10.5度以內，在3.1~5GHz，增益為4~11.9dB，線性度上，IP1dB為-12~-16.9 dBm，IIP3為-0.5~-5.5 dBm，Noise Figure為5.5~7.9 dB。
3.1~5 GHz寬頻升頻混波器，主要是使用Gilbert Cell架構，加上Multi-Gate使此電路具有高線性度的特性，量測結果顯示在頻段內，轉換增益為4.6~5.1dB，線性度上，IP1dB為-11.4~-13.1 dBm，IIP3為-2.6~-5.1 dBm，LO-RF Isolation為-19~-24 dB。

The design and implementation of the Radio Frequency (RF) front-end circuits transceiver CMOS chip for the low band (3.1~5GHz) of Ultra-wide Band are presented. The RF front-end circuits includes active balun、Low noise amplifier with on chip active balun and up conversion mixer. The chips are implemented in TSMC 0.18μm 1P6M provided by National Chip Implementation Center (CIC).The chips are measured on PCB with bonding wire for measured.
The 3.1~5 GHz wide band active balun adopts cascade structure with NMOS and PMOS transistors. This architecture has low power consumption because current reused technique. The measure result shows that in frequency band, the gain imbalance and phase errors are less than 2 dB and 10 degree, respectively. Moreover, the input output return loss are below -10 dB, the IP1dB is-3~-3.5 dBm.IIP3 is 10.6~11.4 dBm, noise Figure is 9.9~13 dB.
The other design is 3.1~5 GHz wide band Low Noise Amplifier (LNA) with on chip active balun. The LNA adopts cascade topology and Single-Stage Multi-Gated Transistors to enhance the performance. The measure results that in frequency band. The gain imbalance and phase error are less than 1.2 dB and 10.5 degree, respectively. The gain is 4~11.9dB,.The output return loss is less than -10dB.The IP1dB is-12~-16.9 dBm，IIP3 is -0.5~-5.5dBm. Noise Figure is 5.5~7.9 dB.
The Gilbert Cell structure is adopted to implement the 3.1~5 GHz wideband up conversion mixer design. The measure result shows that in frequency band, the conversion gain is 4.6~5.1dB, IP1dB is -11.4~-13.1 dBm, IIP3 is -2.6~-5.1 dBm, and LO-RF Isolation is -19~-24 dB.

第一章 緒論 8
1.1 UWB研究背景與動機 8
1.2 UWB的定義 8
1.3 UWB的特性 8
1.4 UWB的系統架構 8
1.5 DS-CDMA與MB-OFDM的技術比較 8
第二章 射頻系統架構與概念 8
2.1接收機簡介 8
2.2接收機架構 8
2.2.1超外差式接收機(Super-Heterodyne receiver) 9
2.2.2鏡像拒斥接收機(Imaged-reject receiver) 8
2.2.3直接降頻接收機(Direct conversion receiver) 8
2.3基本概念 8
2.3.1雜訊(Noise) 8
2.3.1.1熱雜訊(Thermal Noise) 8
2.3.1.2 散彈雜訊(Shot Noise) 8
2.3.1.3 閃爍雜訊(flicker Noise) 8
2.3.1.4雜訊指數(Noise Figure) 8
2.3.3 非線性特性 8
2.3.3.1 1dB增益壓縮點(1dB compression Point) 8
2.3.3.2三階截距點 8
第三章 CMOS 主動式分相器 8
3.1簡介 8
3.2電路架構 8
3.3模擬與量測結果 8
3.3.1 模擬結果 8
3.3.2 量測結果 8
第四章 低雜訊放大器整合主動分相器 8
4.1簡介 8
4.2最佳電晶體寬度選擇 8
4.3輸入阻抗匹配 8
4.4線性化技巧[26][27] 8
4.5 電路架構[28] 8
4.6模擬與量測結果 8
4.6.1模擬結果 8
4.6.2 量測結果 8
第五章 CMOS 升頻混波器 8
5.1 簡介 8
5.1.1 被動式混波器 8
5.1.2 主動式混波器 8
5.1.2.1 單平衡混波器 8
5.1.2.2 雙平衡混波器 8
5.2 電路架構[29] 8
5.3模擬與量測結果 74
5.3.1模擬結果 74
5.3.2量測結果 77
第六章 結論 83
參考文獻 84

[1]李志常，高線性度RF CMOS低雜訊放大器之最佳閘極寬度設計與RF CMOS之新型相位雜訊模型，國立中正大學電機工程研究所碩士論文,民國93年。
[2] B. Razavi, RF Microelectronics, Prentice Hall, Upper Saddle River,NJ,1998.
[3]呂育澤，2.4GHz低必vCMOS發射晶片及必v放大器之設計，國立中正大學電機工程研究所碩士論文 民國93年。
[4] A.A. Abidi, “Direct-conversion Radio for Digital communications,” IEEE Journal of Solid-State Circuits, vol. 30, No. 12,pp.1399-1410, December 1995.
[5] B. Razavi, Design of Analog CMOS Integrated Circuit, International Edition, Boston : McGraw-Hill, 2001.
[6] Y. Tsividis, Operation and Modeling of the MOS Transistor, Second Edition, Boston: McGraw-Hill,1999.
[7] A.A. Abidi, “High-frequency noise measurements on FETs with small dimensions,” IEEE Trans. Electron Devices, vol. 33, pp. 1801-1805, Nov. 1986.
[8] A. vander Ziel, Noise in Solid State Devices and Circuits. New York: Wiley, 1986.
[9] Y. Tsividis, Operation and Modeling of the MOS Transistor, Second Edition, Boston: McGraw-Hill, 1999.
[10] H. T. Friis, “Noise figure of radio receivers,” Proc. IRE, vol. 32, pp. 419-422, July 1944.
[11] Kian Sen Ang, Yoke Choy Leong and Chee IILow Lee, “Analysis and Design of Minaturized Lumped-Distributed Impedance-Transforming Baluns,”IEEE Trans. Microwave Theory Tech, Vol.51, No.3, March 2003.
[12] C.W. Tang and C.Y. Chang, “A semi-lumped balun fabricated by low temperature co-fired ceramic,” in IEEE MTT-S Int. Microwave Symp Digest,pp.22201-2204, 2002.
[13] Yeong J.Yoon, Yicheng Lu, Robert C.Frye, Peter and R.Smith , “Spiral Transmission-Line Baluns for RF Multichip Module Packages,” in IEEE Transactions ON Advanced packaing,Vol.22, No. 3,August 1999.
[14] A.H Baree and I.D Robertson, “Analysis and Design of Multi-Octave MMIC Active Baluns Using a Distributed Amplifier Gate Line Termination Technique,” in IEEE Microwave and Millimeter-Wave Monolithic Circuits Symposium, 1995.[15] M.C. Tsai, M.J. Schindler, W. Struble, M. Ventresca, R. Binder, R. Waterman, and D. Danzilio, “A Compact Wideband Balanced Mixer,” in IEEE MTT-S Digest, 1994.
[16] Huainan Ma, Sher Jiun Fang, Fujiang Lin and Hiroshi Nakamura, “Novel active differential Phase Splitters in RFIC for wireless applications,” IEEE Radio Frequency Integrated Circuits Symposium, 1998.[17] D. K. Shaeffer and T. H. Lee, “A 1.5-V 1.5-GHz CMOS low noise amplifier,” IEEE J. of Solid-State Circuits, vol. 32, No. 5, pp. 745-759, May 1997.
[18] S. Long, “Fundamentals of Mixer Design,” Hewlett Packard Design Semiar, 2001.
[19] Barrie Gilbert, The Multi-tanh Principle: “A Tutorial overview”, IEEE J. Solid-State Circuits”, vol.33, pp 2-17, January 1998.
[20] Sapone G., Palmisano G., “A 0.25-μm CMOS Low-Power Up-Conversion Mixer for 3.1-5 GHz Ultra-Wideband Applications ” IEEE conf, vol 12, pp 457–460 June 2006.
[21] Tae Wook Kim, Bonkee Kim, and Kwyro Lee, “Highly Linear Receiver Front-End Adopting MOSFET Transconductance Linearization by Multiple Gated Transistors,” IEEE J. Solid State Circuits, vol 39, no. 1, Jan 2004.
[22] Keng Leong Fong, “High-Frequency Analysis of Linearity Improvement Technique of Transconductance Stage Using a Low-Frequency-Trap Network,” IEEE Journal of Solid-State Circuits, vol. 35, no.8, Jan 200.
[23] D.K. Shaeffer and Thomas H. Lee, “A 1.5V, 1.5GHz CMOS Low Noise Amplifier,” IEEE J. Solid-State Circuits, vol. 32, pp. 745-759, May 1997.
[24] Ta-Tao Hsu, Chien-Nan Kuo, “Low Power 8-GHz Ultra-Wideband Active Balun,” IEEE Silicon Monolithic Integrated Circuit in RF System, pp. 365-368 Jan, 2006.
[25] Munenari Kawashima, Tadao Nakagawa, and Katsuhiko Araki, “A Novel Broadband Active Balun,” European Microwave Conference, 2003.
[26] V. Aparin and L.E. Larson, “Modified Derivative Superposition Method for Linearizing FET Low-Noise Amplifiers,” IEEE Trans. On theory and techniques, Vol. 53, No 2, Feb, 2005.
[27] V. Aparin and L. E. Larson, “Linearization of monolithic LNA’s using low-frequency low-impedance input termination,” in Eur. Solid-State Circuits Conf., pp.137-140, Sep. 2003.
[28] 賴俊呈，應用於超寬頻系統之低雜訊放大器與主動分相器及應用於5.2GHz接收機之射頻前端電路設計，國立中正大學電機工程研究所碩士論文,民國95年。
[29] Alam, S.K., DeGroat, J., “A 2 GHz high IIP3 down-conversion mixer in 0.18-μm CMOS,” IEEE Silicon Monolithic Integrated Circuits in RF Systems, pp 194-197, Jan 2006.