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研究生:古世隆
研究生(外文):Shih-Lung Ku
論文名稱:去同步化控制電路之FPGA實現
論文名稱(外文):FPGA Implementation of a Desynchronized Control Circuit
指導教授:陳仁德陳仁德引用關係
指導教授(外文):Ren-Der Chen
學位類別:碩士
校院名稱:長庚大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:中文
論文頁數:43
中文關鍵詞:非同步管線架構去同步化握手協定
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管線架構(pipeline)是我們耳熟能詳的電路架構之一,不過,我們常常會利用全域時脈去操控所有的儲存裝置,使它成為一個同步管線電路;但是同樣的管線電路我們卻以非同步的方法實現的話,將會有意想不到的好處。非同步管線電路除了能夠去除掉全域時脈所帶來的問題,如時脈歪斜(clock skew)、必須以最慢的速度在工作等等。因此,本篇論文就是利用非同步電路常用的握手協定(Handshake Protocol)的想法設計出控制電路,並且用該電路來操控每一級的儲存裝置,讓每一級都能以該級的最大延遲作為運算時間,而不必像同步管線電路要以全域時脈做為運算時間。然而在全域時脈已去除之後,那麼時脈歪斜的問題也就迎刃而解了。因此我們要做的就是完成控制電路的設計,以及計算每一級的最大延遲時間,並且將原本的管線電路中的每一級的組合電路重新做獨立的設計。在本篇論文的最後會用一個DES加密演算法的管線架構的電路以及一個四級的16-bit的Booth乘法器做為實驗對象,用以證明非同步控制電路的正確性。
第一章 簡介………………………………………………………1
1.1 研究動機……………………………………………………2
1.2 設計概念………………………………………………………4
第二章 非同步電路的溝通行為…………………………………7
2.1 握手通訊協定…………………………………………………7
2.2 單級控制電路的握手通訊協定………………………………10
2.3 多級控制電路的握手通訊協定………………………………13
第三章 非同步的栓鎖器控制電路………………………………15
3.1 簡單四相握手通訊協定的控制電路…………………………16
3.2 Semi-decoupled四相握手通訊協定控制電路……………17
第四章 控制電路的時序分析……………………………………21
4.1 考慮電路延遲時間的分析……………………………………21
第五章 實驗結果…………………………………………………24
5.1 DES加密演算法………………………………………………24
5.2 Booth乘法器…………………………………………………31
5.2.1 Booth乘法器時序驗證……………………………………31
5.2.2 Booth乘法器FPGA驗證……………………………………34
第六章 結論…………………………………………………………41
參考文獻………………………………………………………………42
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[7]P. Day and J. V. Woods, "Investigation into micropipeline latch design styles," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 3, no. 2, pp. 264-272, June 1995.
[8]R. Dobkin, R. Ginosar, and C. P. Sotiriou, "Data synchronization issues in GALS SoCs," in Proc. 10th Int. Symp. Asynchronous Circuits and Systems, 2004, pp. 170-180.
[9]S. B. Furber and P. Day, "Four-phase micropipeline latch control circuits," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 4, no. 2, pp. 247-253, June 1996.
[10]S. B. Furber and J. Liu, "Dynamic logic in four-phase micropipelines," in Proc. 2th Int. Symp. Advanced Research in Asynchronous Circuits and Systems (ASYNC'96), 1996, pp. 18-21.
[11]http://www.altera.com
[12]http://www.opencores.org
[13]J. Kessels, A. Peeters, P. Wielage, and S.-J. Kim, "Clock synchronization through handshake signalling," in Proc. 8th Int. Symp. Asynchronous Circuits and Systems, 2002, pp. 59-68.
[14]R. Kol and R. Ginosar, "A doubly-latched asynchronous pipeline," in Proc. Int. Conf. Computer Design (ICCD), 1996, pp. 706–711.
[15]J. Muttersbach, "Globally-asynchronous locally-synchronous architectures for VLSI systems," Ph.D. dissertation, ETH, Zurich, 2001.
[16]M. Najibi, K. Saleh, M. Naderi, H. Pedram, and M. Sedighi, "Prototyping globally asynchronous locally synchronous circuits on commercial synchronous FPGAs," in Proc. 16th IEEE Int. Workshop on Rapid System Prototyping (RSP), 2005, pp. 63-69.
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