# 臺灣博碩士論文加值系統

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 傳統的能隙參考電壓電路中，輸出電壓是雙載子電晶體中基極-射極接面電壓VBE與熱電壓(thermal voltage)VT (KT/q) 乘以一個常數的總和，因此輸出電壓大約為1.25V，而這輸出電壓限制了1V以下的操作。此外，1V以下的能隙參考電壓電路，則受限於BJT與MOS的臨界電壓(VBE=0.7V,VTH=0.5V by TSMC 0.18um process)的限制，無法在0.5V以下工作。本論文提出了一個可操作在0.5V以下的CMOS參考電壓電路，所提出的電路中，主架構為一Widlar電流鏡，將所有電晶體偏壓在弱反轉區(VGS=0.25V)，且其弱反轉區的VGS會隨著溫度遞減，並藉由正負溫度係數電壓與大電阻的組合，產生一個與溫度無關的參考輸出電壓。佈局後模擬結果為VDD=0.5V,Vref=242mV，當溫度從-40度增加到120度C時，參考輸出電壓也只有1.25mV的變化，溫度補償的漂移為57.85ppm。整體架構實施只需5顆電晶體與4個電組，而可操作的最低工作電壓為0.45V。
 For a conventional Bandgap voltage reference circuit, the output voltage (Vref) is the BJT base-emitter junction voltage (VBE) plus the thermal voltage VT(KT/q) multiplied by a constant. Therefore, its value is about 1.25V, which limits a low supply voltage operation below 1V. Moreover, low voltage Bandgap voltage reference circuits are limted to the threshold voltages of BJT and MOS (VBE=0.7V,VTH=0.5V by TSMC 0.18um process), therefore they can not work under 0.5V. This thesis proposes a CMOS voltage reference circuit, which can successfully operate with sub-0.5V supply voltage.In the proposed circuit,the major structure is a Widlar current mirror. All transistors are biased in subthreshold region and VGS in subthreshold region decreases with the temperature. By combining positive and negative temperature coefficient voltages and large resistances, the reference voltage independent of the temperature can be obtained.Based on post-layout simulations(VDD=0.5V,Vref=242mV), the variation of the reference voltage is about 1.25mV(57.85ppm) in the temperature range from -40 to 120°C. There are only 5 transistors and 4 resistors in the CMOS voltage reference circuit structure. And the lowest working voltage is 0.45V.
 指導教授推薦書口試委員審定書授權書……………………………………………………………………………………-iii-誌謝………………………………………………………………………………………-iv-中文摘要…………………………………………………………………………………-v-英文摘要…………………………………………………………………………………-vi-目錄………………………………………………………………………………………-vii-圖目錄……………………………………………………………………………………-x-表目錄……………………………………………………………………………………-xvi-第一章 緒論……………………………………………………………………………-1- 1.1 研究背景與動機………………………………………………………-1- 1.2參考電壓源的應用……………………………………………………-3- 1.2.1電壓整流器……………………………………………………………-3- 1.2.2電壓偵測器………………………………………………-3- 1.2.2類比數位轉換器(ADC)………………………………………………-4- 1.3本篇論文架構之應用於生醫儀表放大器……………………………-5- 1.4 論文結構說明…………………………………………………………-7-第二章 能隙參考電壓設計與原理……………………………………………………-8- 2.1基本能隙參考電壓源理論……………………………………………-8- 2.2基本能隙參考電壓源理論推導………………………………………………-9- 2.3傳統能隙參考電壓源分析……………………………………………-14- 2.3.1傳統bandgap參考電壓源一些非理想效應…………-16- 2.3.1.1運算放大器的有限電壓增益……………………………-16- 2.3.1.2運算放大器之漂移電壓(offset voltage)…………-19- 2.3.1.3 Bandgap參考電壓源核心電路的元件匹配……………-20- 2.3.2傳統bandgap參考電壓源不能操作在1v以下的原因……-21- 2.4近年來能隙參考電壓元電路設計………………………………………-22- 2.4.1電阻式補償的參考電壓源…………………………………-23- 2.4.1.1類似傳統式……………………………………………………-23- 2.4.1.2非傳統架構……………………………………………………-39- 2.4.2非電阻式補償的參考電壓源………………………………-44-第三章 一伏特以下低功率參考電壓源設計……………………………………………-56- 3.1一伏特以下無電阻參考電壓源討論………………………………………-56-3.2零點五伏特以下參考電壓源分析與設計……………………………………………-60- 3.2.1 VGS與溫度T呈負相關之討論使用弱反轉區MOS……………………-61- 3.2.2溫度補償方法分析使用弱反轉區MOS…………………………………-63- 3.2.3使用CDB技術降低Vdd工作電壓………………………………………-72- 3.2.4零點五伏參考電壓源設計……………………………………………………-87-第四章 電路模擬結果、比較、佈局與量測……………………………………………-94- 4.1零點五伏特參考電壓源電路模擬與比較………………………………-94- 4.2零點五伏特參考電壓源電路佈局………………………………………-103- 4.3零點五伏特參考電壓源電路佈局後模擬………………………………-112- 4.4零點五伏特參考電壓源電路量測方法…………………………………-117-第五章 結論與未來建議…………………………………………………………………-119- 5.1結論………………………………………………………………………-119- 5.2未來建議…………………………………………………………………-120-參考文獻…………………………………………………………………………………-121-
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 1 一伏特以下之低功率CMOS能隙參考電壓電路設計

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 1 一伏特以下之低功率CMOS能隙參考電壓電路設計 2 操作於弱反轉層場效電晶體之極低功率損耗與極小面積CMOS參考電壓之設計與實現 3 參考電壓電路與鎖相迴路電路 研究與實現 4 薄膜電晶體的溫度係數模型以及玻璃基板上具溫度補償功能之參考電壓電路 5 無電阻式CMOS參考電壓電路 6 具溫度漂移校準之純CMOS參考電壓電路及改良式無外部電容之LDO穩壓器 7 生醫訊號應用的高共模拒斥比電流式儀表放大器 8 運用次臨界特性之低電壓CMOS參考電壓電路設計 9 低溫度係數之能隙參考電壓電路設計 10 低功率參考電壓源電路及LDO研究與實現 11 高速低電壓差動訊號之傳接器及正比於絕對溫度的參考電壓電路設計 12 CMOS低壓降穩壓積體電路之設計 13 生醫訊號應用的高解析和差調變器之低功率數位濾波器晶片設計 14 應用於心律調節器之超低功率帶通濾波器 15 一階及二階帶差電壓參考電路設計及誤差分析

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