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研究生:陳志瑋
研究生(外文):Zhi-Wei Chen
論文名稱:對於訊號完整之可靠性導向電源供應系統設計
論文名稱(外文):Reliability Driven Power Supply System Design for Signal Integrity
指導教授:顏金泰
指導教授(外文):Jin-Tai Yan
學位類別:碩士
校院名稱:中華大學
系所名稱:資訊工程學系(所)
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:英文
論文頁數:48
中文關鍵詞:電源拓墣可靠度訊號完整
外文關鍵詞:power topology designreliabilitysignal integrity
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在目前設計超大型積體電路環境中,隨著晶片設計密度的提高,使得電源供應網路中電流需求的增加;隨著製程的進步,金屬導線之線寬越來越細,使得導線上的阻抗值變大,使得電源供應網路供應足夠的電流源變得困難許多。在本篇論文中,在己知版面規劃上各電流需求點之位置的情況下,我們使用一個己知版面的階層式電源四分格架構來建構電源供應網路,這種方式可以動態的建立電源供應網路拓樸及滿足區域性高電流密度之分佈的版面規劃設計。基於己知版面規劃之階層式電源四分格架構下電源供應系統下,我們進一步提出一最佳化之電路分析方式來精確的求得電源供應系統中,所有參考點之電壓值及參考分歧之電流值。再者,為了滿足此架構下的所受到之電位衰退及電子遷移限制,我們提出一個反覆式二階段的方法,去設計在階層式電源四分格架構下,以可靠度導向之電源供應網路設計。在供應足夠之電源需求情況下,安排有限的電源墊及電源線資源調整,來達到所有參考分歧上之電流密度滿足電子遷移的限制及所有參考點滿足電位衰退的限制在實驗結果中,我們可以看到此一反覆式二階段方法可以在有限制電源墊之使用數量情況下,可以節省更多的電源繞線資源去解決電位衰退的問題,並能在合理的執行時間下完成。
In modern VLSI chips, the increase in chip densities yields an increase in the currents drawn from the power network, and the increase in wire resistances makes the current delivery from the power network difficult. Based on the locations of the current requirements in a given floorplan, the floorplan–aware hierarchical power quad-grids(FHPQGs) are used to dynamically construct the topology of power grids to meet the local distribution of high current densities in the floorplan. Based on the geometrical structure in the proposed FHPQGs, an optimal circuit analysis approach is further proposed to accurately find the currents of all the reference branches and the voltages of all the reference nodes in the FHPQGs. Given a floorplan with hierarchical power quad-grids(HPQGs), the IR-drop constraint and the electro-migration constraint, an iterative two-phase approach is proposed to design reliability-driven HPQGs to assign limited power pads and power wires to supply the required current and satisfy the current density constraint for any power branch and the IR-drop constraint for any power node with minimizing total wiring area. The experimental results show that the iterative two-phase approach uses less total wiring area under limited power pads to release all the IR-drop constraints in reasonable CPU time for the tested examples.
Chap1. Introduction Chap 2. Motivation and Problem Formulation 2.1 Motivation 2.2 Problem Formulation Chap 3. Floorplan-aware Hierarchical Power Quad-Grids Chap 4. Optimal Circuit Analysis in FHPQGs 4.1 Equivalent-voltage features exist in the internal power grids 4.2 Equivalent-voltage features exist in the external power ring 4.3 Equivalent-voltage features exist on ‘+’-type power node Chap 5. Simultaneous Assignment of Power Pads and Wires for Reliability-Driven HPQGs 5.1 IR-drop Avoidance via Simultaneous Assignment of Power Pads and Wires 5.1.1 Separation of hierarchical power quad-grids for power pads 5.1.2 Integration of voltage-effect clusters after power pad reassignment 5.1.3 Linear Voltage Scaling Phase 5.2 Reliability Maintenance via Assignment of Power Wires 5.2.1 Linear Current Scaling Phase Chap 6. Experimental Results Chap 7. Conclusions and Further Work References
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