在目前設計超大型積體電路環境中，隨著晶片設計密度的提高，使得電源供應網路中電流需求的增加；隨著製程的進步，金屬導線之線寬越來越細，使得導線上的阻抗值變大，使得電源供應網路供應足夠的電流源變得困難許多。在本篇論文中，在己知版面規劃上各電流需求點之位置的情況下，我們使用一個己知版面的階層式電源四分格架構來建構電源供應網路，這種方式可以動態的建立電源供應網路拓樸及滿足區域性高電流密度之分佈的版面規劃設計。基於己知版面規劃之階層式電源四分格架構下電源供應系統下，我們進一步提出一最佳化之電路分析方式來精確的求得電源供應系統中，所有參考點之電壓值及參考分歧之電流值。再者，為了滿足此架構下的所受到之電位衰退及電子遷移限制，我們提出一個反覆式二階段的方法，去設計在階層式電源四分格架構下，以可靠度導向之電源供應網路設計。在供應足夠之電源需求情況下，安排有限的電源墊及電源線資源調整，來達到所有參考分歧上之電流密度滿足電子遷移的限制及所有參考點滿足電位衰退的限制在實驗結果中，我們可以看到此一反覆式二階段方法可以在有限制電源墊之使用數量情況下，可以節省更多的電源繞線資源去解決電位衰退的問題，並能在合理的執行時間下完成。

In modern VLSI chips, the increase in chip densities yields an increase in the currents drawn from the power network, and the increase in wire resistances makes the current delivery from the power network difficult. Based on the locations of the current requirements in a given floorplan, the floorplan–aware hierarchical power quad-grids(FHPQGs) are used to dynamically construct the topology of power grids to meet the local distribution of high current densities in the floorplan. Based on the geometrical structure in the proposed FHPQGs, an optimal circuit analysis approach is further proposed to accurately find the currents of all the reference branches and the voltages of all the reference nodes in the FHPQGs. Given a floorplan with hierarchical power quad-grids(HPQGs), the IR-drop constraint and the electro-migration constraint, an iterative two-phase approach is proposed to design reliability-driven HPQGs to assign limited power pads and power wires to supply the required current and satisfy the current density constraint for any power branch and the IR-drop constraint for any power node with minimizing total wiring area. The experimental results show that the iterative two-phase approach uses less total wiring area under limited power pads to release all the IR-drop constraints in reasonable CPU time for the tested examples.

Chap1. Introduction Chap 2. Motivation and Problem Formulation 2.1 Motivation 2.2 Problem Formulation Chap 3. Floorplan-aware Hierarchical Power Quad-Grids Chap 4. Optimal Circuit Analysis in FHPQGs 4.1 Equivalent-voltage features exist in the internal power grids 4.2 Equivalent-voltage features exist in the external power ring 4.3 Equivalent-voltage features exist on ‘+’-type power node Chap 5. Simultaneous Assignment of Power Pads and Wires for Reliability-Driven HPQGs 5.1 IR-drop Avoidance via Simultaneous Assignment of Power Pads and Wires 5.1.1 Separation of hierarchical power quad-grids for power pads 5.1.2 Integration of voltage-effect clusters after power pad reassignment 5.1.3 Linear Voltage Scaling Phase 5.2 Reliability Maintenance via Assignment of Power Wires 5.2.1 Linear Current Scaling Phase Chap 6. Experimental Results Chap 7. Conclusions and Further Work References

[1] T. Mitsuhashi and E. S. Kuh, “Power and Ground Network Topology Optimization for Cell Based VLSIs,” IEEE/ACM Design Automation Conference, pp. 524–529, 1992. [2] H. Cai, “Multi-pads Single Layer Power Net Routing in VLSI Circuit,” IEEE/ACM Design Automation Conference, pp. 183–188, 1988. [3] J. Oh and M. Pedram, “Multi-pad Power/Ground Network Design for Uniform Distribution of Ground Bounce,” IEEE/ACM Design Automation Conference, pp.287-290, 1998. [4] J. Singh and S. S. Sapatnekar, “Topology Optimization of Structured Power/Ground Networks,” ACM International Symposium on Physical Design, pp.116-123, 2004. [5] J. Singh and S. S. Sapatnekar, “A Fast Algorithm for Power Grid Design,” ACM International Symposium on Physical Design, pp.70-77, 2005. [6] X. D. Tan, C. J. Shi, D. Lungeanu, J. C. Lee and L. P. Yuan., “Reliability-Constrained Area Optimization of VLSI Power/Ground Networks Via Sequence of Linear Programmings,” IEEE Transactions on Computer-Aided Design, Vol.22, No.12, pp.1678–1684, 1993. [7] X. D. S. Tan and C. J. R. Shi, “Fast Power/Ground Network Optimization Based on Equivalent Circuit Modeling,” IEEE/ACM Design Automation Conference, pp. 550–554, 2001. [8] X. Wu et al, “Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques,” IEEE/ACM International Conference on Computer-Aided Design, pp. 153–157, 2001. [9] T. Wang and C. C. Chen, “Optimization of the Power/Ground Network Wire-Sizing and Spacing Based on Sequential Network Simplex Algorithm,” IEEE International Symposium on Quality Electronic Design, pp. 157–162, 2002. [10] H. Su, K. H. Gala, and S. S. Sapatnekar, “Fast Analysis and Optimization of Power/Ground Networks,” IEEE/ACM International Conference on Computer-Aided Design, pp. 477–480, 2000. [11] H. H. Chen and D. D. Ling, “Power Supply Noise Analysis Methodology for Deep-Sub-micron VLSI Chip Design,” IEEE/ACM Design Automation Conference, pp. 638–643, 1997. [12] S. Zhao, K. Roy and C. K. Koh, “Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning,” IEEE Transactions on Computer-Aided Design, Vol. 21, No. 1, pp.81-92, 2002. [13] J. T. Yan, Z. W. Chen and M. Y. Wu, “Area-Driven Decoupling Capacitance Allocation in Noise-Aware Floorplan for Signal Integrity,” IEEE International Symposium on Circuits and Systems, 2007. [14] H. Kriplani, F. Najm, and I. Hajj, “Pattern Independent Maximum Current Estimation in Power and Ground Buses of CMOS VLSI Circuits: Algorithms, Signal Correlations, and Their Resolution,” IEEE/ACM International Conference on Computer-Aided Design, pp. 998–1012, 1995. [15] V. A. Patel, “Numerical Analysis,” Harcourt Brace College Publishers, 1994. [16] J. Cong, “An Interconnect-Centric Design Flow for Nanometer Technologies,” Proceedings of the IEEE, vol. 89, pp. 477–480, 2000. [17] X. D. Tan, C. J. Shi, D. Lungeanu, J. C. Lee and L. P. Yuan., “Reliability-Constrained Area Optimization of VLSI Power/Ground Networks Via Sequence of Linear Programmings,” IEEE/ACM Design Automation Conference, pp.156–161, 1999. [18] H. Su, K. H. Gala, and S. S. Sapatnekar, “Fast Analysis and Optimization of Power/Ground Networks,” IEEE/ACM International Conference on Computer-Aided Design, pp. 477–480, 2000. [19] H. H. Chen and D. D. Ling, “Power Supply Noise Analysis Methodology for Deep-Sub-micron VLSI Chip Design,” IEEE/ACM Design Automation Conference, pp.638–643, 1997. [20] J. T. Yan, C. W. Wu and Y. H. Chen, “Wiring Area Optimization in Floorplan-Aware Hierarchical Power Grids,” IEEE International Symposium on Circuits and Systems, pp.1366-1369, 2005. [21] S. Ghowdhury. “An Automated Design of Minimum-Area IC Power/Ground Nets,” IEEE/ACM Design Automation Conference, pp.223-229, 1987. [22] C. C. Wong, “Flip Chip connection Technology”, in Multichip Module Technologies and Alternatives: The Basics, Edited by D. A. Doane and P. D. Franzon, Van Nostrand Reinhold, 1993. [23] T. Mitsuhashi and E. S. Kuh “Power and Ground Network Topology Optimization for Cell Based VLSIs,” IEEE/ACM Design Automation Conference, pp.524-529, 1992. [24] L. Schaper, S. Ang, Y. Low, and D. Oldham, “The Interconnected Mesh Power System (IMPS) MCM Topology,” Proceedings of the IEEE, pp.231-234, 1994. [25] T. Sato, M. Hashimoto and H. Onodera, ”Successive pad assignment algorithm to optimize number and location of Power supply using incremental matrix inversion” IEEE Asia and South Pacific Design Automation Conference, pp. 723-728, 2005. [26] H Chen, CK Cheng, AB Kahng, M Mori, and Q Wang “Optimal Planning for Mesh-Based Power Distribution,” ACM International Symposium on Physical Design, pp.60-65, 2005. [27] J. T. Yan, K. P. Lin and Y.H. Chen, “Decoupling Capacitance Allocation in Noise-Aware Floorplanning based on DBL Representation,” IEEE International Symposium on Circuits and Systems, pp. 2219-2222, 2005. [28] M. Zhao, R.V. Padnda, S. S. Sapatnkar, and D. Blaauw, “Hierarchical Analysis of Power Distribution Networks,” IEEE/ACM Design Automation Conference, pp. 150-155, 2000. [29] H. Su, J. Hu, S. S. Sapatnekar and S. R. Nassif, “Congestion-driven Codesign of Power and Signal Networks,” IEEE/ACM Design Automation Conference, pp. 64-69, 2002. [30] S. W. Wu and Y. W. Chang, “Efficient Power/Ground Network Analysis for Power Integrity-Driven Design Methodology,” IEEE/ACM Design Automation Conference, pp. 177-180, 2004. [31] M. Zhao, Y. Fu, V. Zolotov, S. Sundareswaran, and R. Panda, “Optimal Placement of Power Supply Pads and Pins,” IEEE/ACM Design Automation Conference, pp. 165-170, 2006. [32] K. Wang and M. M. Sadowska. “On-chip Power Supply Network Optimization using Multigrid-based Technique,” IEEE/ACM Design Automation Conference, pp. 113-118, 2004. [33] A. V. Mezhiba and E. G. Friedman, “Inductance/Area/Resistance Tradeoffs in High Perforinance Power Distribution Grids”, IEEE International Symposium on Circuits and Systems, pp. 101-104, 2002. [34] S. Boyd, L. Vandenberghe, A. El Gamal and S. Yun, “Design of Robust Global Power and Ground Networks”, ACM International Symposium on Physical Design, pp. 60-65, 2001. [35] S. R. Nassif and J. N. Kozhaya, “Fast power grid simulation,” IEEE/ACM Design Automation Conference, pp.156-161, 2000. [36] J. N. Kozhaya, S. R. Nassif, and F. N. Najm, “Multigrid- like Technique for Power Grid Analysis,” IEEE/ACM International Conference on Computer Aided Design, pp. 480-487, 2001.