臺灣博碩士論文加值系統

本篇論文對鍺濃度為20%的矽鍺虛擬基板，利用直流電性與雜訊分析探討在不同矽覆層厚度下的P 型應變矽金氧半場效電晶體的電性行為。應變矽元件是以磊晶製程將矽沉積於矽鍺虛擬基板上，因此應變矽薄膜或底下的矽鍺虛擬基板品質好壞將直接影響元件特性。當矽覆層的厚度為10nm 時，應變矽太薄不足以阻擋鍺外擴到二氧化矽介面，大多數的載子將通過載子移動率較低的鬆弛矽鍺層，導致較少的載子通過矽通道，造成載子移動率的下降。由本論文實驗量測分析可知因為製程上的缺陷，使得伸張應變矽在矽鍺虛擬基板上的特性並未達到預期的電流增益。

In this thesis, we analyse DC characteristics and 1/f noise analysis strained-Si PMOSFET for different Si-Cap layer thickness and 20% Ge content of SiGe virtual substrate. Strained-Si is grown on SiGe virtual substrate using epitaxial Si and the quality of strained-Si thin film directly influence the characteristic of the device. When the thickness of Si-Cap layer is 10nm, it is not enough to prevent the Ge out-diffusion phenomenon which Ge diffuses into SiO2. Under this thickness of Si-Cap layer, the device will produce an additional travel pass for most holes through the low-mobility relaxed SiGe and result in poor carrier confinement within the Si channel, and low mobility. Because of process defect, tensile strained-Si of SiGe virtual substrate has not been enhanced in current characteristic.

目錄
論文摘要(中文)....................................... i
論文摘要(英文)....................................... ii
致謝................................................. iii
目錄................................................. iv
表目錄............................................... vi
圖目錄............................................... vii
第一章 緒論.......................................... 1
　1-1 背景與動機.................................... 1
　1-2 論文架構...................................... 4
第二章 應變矽P 型金氧半場效電晶體.................... 9
　2-1 應變矽的材料特性簡介.......................... 9
　2-2 應變矽金氧半場效電晶體元件簡介................ 11
第三章 元件結構與量測................................ 21
　3-1 應變矽金氧半場效電晶體的製程.................. 21
　3-2 量測實驗的設計與量測機台簡介.................. 23
第四章 直流電性量測與分析............................ 30
　4-1 實驗的量測與分析.............................. 30
　4-2 C-V特性曲線................................... 31
　4-3 I-V特性曲線................................... 36
　4-4 應變矽元件小尺寸時之特性表現.................. 42
第五章 雜訊量測與分析................................ 65
　5-1 雜訊的形成.................................... 65
　5-2 MOS雜訊理論發展與論文回顧..................... 70
　5-3 低頻1/f 雜訊頻譜量測結果分析.................. 72
第六章 結果與討論.................................... 80
第七章 未來展望...................................... 81
參考文獻............................................. 82

表目錄
表 1-1 不同方向的Strain應力對CMOS的影響.............. 6
表 4-1 元件製程條件與尺寸............................ 48
表 4-2 元件直流電性量測條件.......................... 49

圖目錄
圖 1-1 Strain 應力方向3D 示意圖..................... 7
圖 1-2 應變矽金氧半場效電晶體結構示意圖............. 8
圖 2-1 (a)伸張形變( Tensile strained )與
(b)壓縮形變( Compressive strained ).......... 15
圖 2-2 晶格缺陷所造成的差排( Dislocated )........... 16
圖 2-3 臨界厚度與鍺含量變化圖....................... 17
圖 2-4 能帶間隔差異與鍺含量關係圖................... 18
圖 2-5 矽材料未應變前與受到伸張應變後
導電帶與價電帶的能帶變化簡單示意圖........... 19
圖 2-6 矽材料未應變前與受到壓縮應變後
導電帶與價電帶的能帶變化簡單示意圖........... 20
圖 3-1 漸變組成( Graded Composition )基板........... 26
圖 3-2 元件設計的結構圖............................. 27
圖 3-3 元件結構TEM 圖............................... 28
圖 3-4 量測機台架構................................. 29
圖 4-1 Strained-Si PMOSFET 10μm / 10μm 對應
不同Si-Cap Layer 厚度之C-VG 圖............... 50
圖 4-2 Strained-Si PMOSFET 10μm / 10μm 對應
不同Si-Cap Layer 厚度之介面缺陷密度.......... 51
圖 4-3 Strained-Si PMOSFET 10μm/10μm 對應
不同Si-Cap Layer 厚度之有效載子移動率........ 52
圖 4-4 Strained-Si PMOSFET 10μm/10μm 對應不同
Si-Cap Layer 厚度之有效載子移動率電場比較圖.. 53
圖 4-5 Strained-Si PMOSFET 10μm/10μm 對應不同
Si-Cap Layer 厚度之VGS-IDS轉換特性曲線....... 54
圖4-6 Strained-Si PMOSFET 10μm/10μm 對應不同
Si-Cap Layer 厚度之VDS - IDS輸出特性曲線..... 55
圖 4-7 Strained-Si PMOSFET 10μm/10μm 對應不同
Si-Cap Layer 厚度之IDS增益圖................. 56
圖 4-8 Strained-Si PMOSFET 10μm/10μm 對應不同
Si-Cap Layer 厚度之轉導圖.................... 57
圖 4-9 Strained-Si PMOSFET 10μm / 0.35μm 對應
不同Si-Cap Layer 厚度之VGS-IDS轉換特性曲線... 58
圖 4-10 Strained-Si PMOSFET 10μm / 0.35μm 對應
不同Si-Cap Layer 厚度之轉導圖................ 59
圖 4-11 Strained-Si PMOSFET 10μm / 0.35μm 對應
不同Si-Cap Layer 厚度之VDS-IDS 輸出特性曲線.. 60
圖 4-12 Strained-Si PMOSFET 對應不同Si-Cap Layer 厚度
與不同通道長度之汲極電流比較圖............... 61
圖 4-13 Strained-Si PMOSFET 對應不同Si-Cap Layer 厚度
與不同通道長度之臨界電壓比較圖............... 62
圖 4-14 Strained-Si PMOSFET 對應不同Si-Cap Layer 厚度
與不同通道長度之次臨界織T比較圖............. 63
圖 4-15 Strained-Si PMOSFET 對應不同Si-Cap Layer 厚度
與不同通道長度之汲極引致能障下降比較圖....... 64
圖 5-1 半導體元件中雜訊的分類....................... 76
圖 5-2 半導體元件中雜訊必v頻譜密度的頻譜特性....... 77
圖 5-3 Strained-Si PMOSFET 10μm/10μm 對應
不同Si-Cap Layer 厚度之SID/ID2 圖............ 78
圖 5-4 Strained-Si PMOSFET 10μm/10μm 對應
不同Si-Cap Layer 厚度之SVG 圖................ 79

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