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研究生:張智翔
研究生(外文):Chi Hiang Chang
論文名稱:具即時錯誤偵測及校正能力之有限場多項式基底乘法器設計
論文名稱(外文):Concurrent Error Detection and Correction in Polynomial Basis Multiplier over GF(2^m)
指導教授:邱綺文周復華周復華引用關係
指導教授(外文):Che Wun ChiouFu Hua Chou
學位類別:碩士
校院名稱:清雲科技大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:94
語文別:中文
論文頁數:50
中文關鍵詞:有限場密碼學即時錯誤偵測即時錯誤校正植入錯誤式密碼攻擊法
外文關鍵詞:Finite field arithmeticcryptographyconcurrent error detectionconcurrent error correctionfault based cryptanalysis
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許多密碼系統利用有限場數值運算(Finite field arithmetic)來提升加解密運算速度,而且有限場數值運算適合利用超大型積體電路(VLSI)來實現,更讓有限場數值運算在行動商務上擁有相當大的價值。近年興起的植入錯誤式密碼攻擊法,可以利用破壞硬體加解密電路來快速破解密碼系統,使得密碼系統的安全性及保密性受到極大威脅。為了避免此類型的攻擊最好的解決辦法就是讓密碼系統可以輸出正確的密文(或明文),因此我們提出了具有即時錯誤偵測及校正能力的有限場多項式基底乘法器,僅需少許之額外電路即可有效的抵抗植入錯誤式密碼攻擊法,並且將心臟型陣列乘法器內部的運算結構由傳統的串列架構改為平行處理的架構,可減少許多時間上的延遲以加快運算速度。
Finite field arithmetic has been widely used in many cryptosystems, especially Elliptic Curve Cryptosystem (ECC), for speeding their encryption/decryption processes. Regular structures of finite field arithmetic are suitable for VLSI implementation and then make them very attractive for mobile commerce. The multiplication is the most critical operation in finite field arithmetic operations. Recently, a new cryptanalysis, termed fault based cryptanalysis which deliberates fault injection into cryptographic devices, only require a small amount of side-channel information to break common ciphers. Hence, effective and simple methods for protecting the encryption/decryption circuitry from an attacker are required to ensure that a cryptographic device can output the accurate signature. Therefore, in this paper, a polynomial basis multiplier over GF(2m) with concurrent error detection is presented. Moreover, a polynomial basis multiplier with concurrent error correction is also included. Furthermore, the parallel structure of function cells in the proposed multiplier array is employed for speeding up propagation delay.
中文摘要 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ i
英文摘要 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ ii
致謝 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ iii
目錄 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ v
表目錄 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ vi
圖目錄 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ vii
第一章 前言 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 1
1.1研究背景及目的 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 1
1.2動機 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 4
1.3章節安排 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 5
第二章 背景介紹 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 6
2.1 數論 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 6
2.1.1 同餘 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 6
2.1.2 尤拉定理 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 7
2.1.3 費瑪定理 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 7
2.2 有限場數學 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 8
2.2.1 群 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 8
2.2.2 環 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 8
2.2.3 場 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 9
2.2.4 有限場 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 9
2.2.5 有限場數值基底類型 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 9
2.2.5.1 多項式基底 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 10
2.2.5.2 正規基底 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 10
2.2.5.3 雙重基底 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 10
2.2.6 有限場數值運算 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 11
2.2.6.1 加法運算 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 11
2.2.6.2 乘法運算 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 11
2.2.6.3 乘法反元素運算 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 12
2.2.6.4 除法運算 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 13
2.3 即時錯誤偵測 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 14
2.3.1同位元錯誤偵測 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 14
2.3.2即時錯誤偵測 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 14
2.3.3運算元移位重運算方法∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 14
第三章 平行處理之有限場多項式基底乘法器設計 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 16
3.1平行處理於有限場多項式基底乘法器設計 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 16
3.2各種有限場多項式基底乘法器比較 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 20
3.3 實驗模擬過程及結果 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 21
3.3.1 實驗環境介紹 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 21
3.3.1.1 FPGA簡介∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 21
3.3.1.2 實驗使用環境∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 21
3.3.2 實驗模擬結果∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 23
第四章 具有即時錯誤偵測能力之有限場多項式基底乘法器設計 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 24
4.1具有即時錯誤偵測能力之有限場多項式基底乘法器 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 24
4.2具有即時錯誤偵測能力之有限場多項式基底乘法器效能比較 ∙∙∙∙∙∙∙∙∙∙∙∙∙ 30
4.3 實驗過程及結果∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 31
第五章 具即時錯誤校正能力之有限場多項式基底乘法器設計 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 34
5.1具即時錯誤校正能力之有限場多項式基底乘法器 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 34
5.2具有及不具有即時錯誤校正能力的乘法器效能比較 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 38
5.3實驗過程及結果 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 41
第六章 結論 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 42
參考文獻 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 43
1. http://csrc.nist.gov/encryption/aes
2. F. J. MacWilliams and N. J. A. Sloane, The theory of error-correcting codes, Amsterdam: North-Holland, 1977
3. R. Lidl and H. Niederreiter, Introduction to finite fields and their applications, New York: Cambridge Univ. Press, 1994
4. R. E. Blahut, Fast algorithms for digital signal processing, reading, Mass.: Addison-Wesley, 1985.
5. I. S. Reed and T. K. Truong, “The use of finite fields to compute convolutions”, IEEE Trans. Information Theory, Vol. IT-21, No.2, pp.208-213, March 1975.
6. T. C. Bartee and D. J. Schneider, “Computation with finite fields”, Information and Computing, Vol.6, pp.79-98, Mar. 1963.
7. E. D. Mastrovito, “VLSI architectures for multiplication over finite field GF(2m) ”, Applied Algebra, Algebraic Algorithms, and Error-Correcting Codes, Proc. Sixth Int’l Conf., AAECC-6, T. Mora, ed., Rome, pp.297-309, July 1988.
8. Ç. K. Koç and B. Sunar, “Low-complexity bit-parallel canonical and normal basis multipliers for a class of finite fields”, IEEE Trans. Computers, Vol.47, No.3, pp.353-356, March 1998.
9. C. Y. Lee, “Low complexity bit-parallel systolic multiplier over GF(2m) using irreducible trinomials”, IEE Proc.-Comput. Digit. Tech., Vol.150, No.1, Jan. 2003, pp.39-42.
10. T. Itoh and S. Tsujii, “Structure of parallel multipliers for a class of fields GF(2m) ”, Information and Computation, Vol. 83, 1989, pp.21-40.
11. M. A. Hasan, M. Wang, V. K. Bhargava, “Modular construction of low complexity parallel multipliers for a class of finite fields GF(2m) ”, IEEE Trans. Computers, Vol.41, No.8, August 1992, pp.962-971.
12. C. Y. Lee, E. H. Lu, and J. Y. Lee, “Bit-parallel systolic multipliers for GF(2m) fields defined by all-one and equally-spaced polynomials”, IEEE Trans. Computers, Vol.50, No.5, May 2001, pp.385-393.
13. C. Paar, “A new architecture for a parallel finite field multiplier with low complexity based on composite fields”, IEEE Trans. Computers, Vol.45, No.7, July 1996, pp.856-861.
14. C.W. Chiou, L.C. Lin, F.H. Chou, and S.F. Shu, “Low complexity finite field multiplier using irreducible trinomials”, Electronics Letters, Vol.39, No.24, 27th Nov. 2003, pp.1709-1711.
15. J. L. Massey and J. K. Omura, “Computational method and apparatus for finite field arithmetic”, U.S. Patent Number 4,587,627, May 1986.
16. C. C. Wang, T. K. Truong, H. M. Shao, L. J. Deutsch, J. K. Omura, and I. S. Reed, “VLSI architectures for computing multiplications and inverses in GF(2m) ”, IEEE Trans. Computers, Vol.C-34, No.8, pp.709-717, Aug. 1985.
17. A. Reyhani-Masoleh and M. A. Hasan, “A new construction of Massey-Omura parallel multiplier over GF(2m) ”, IEEE Trans. Computers, Vol.51, No.5, pp.511-520, May 2002.
18. A. Reyhani-Masoleh and M. A. Hasan, “Fast normal basis multiplication using general purpose processors”, IEEE Trans. Computers, Vol. 52, No.11, pp.1379-1390, Nov. 2003.
19. S. Oh, C. H. Kim, J. Lim, and D. H. Cheon, “Efficient normal basis multipliers in composite fields”, IEEE Trans. Computers, Vol.49, No.10, pp.1133-1138, Oct. 2000.
20. H. Fan and Y. Dai, “Key function of normal basis multipliers in GF(2n) ”, Electronics Letters, Vol. 38, No. 23, pp.1431-1432, 7th Nov. 2002.
21. B. Sunar and Ç. K. Koç, “An efficient optimal normal basis type II multiplier”, IEEE Trans. Computers, Vol. 50, No.1, pp.83-87, Jan. 2001.
22. N. Takagi, J.-I. Yoshiki, and K. Takagi, “A fast algorithm for multiplicative inversion in GF(2m) using normal basis”, IEEE Trans. Computers, Vol. 50, No.5, pp.394-398, May 2001.
23. C.Y. Lee and C.W. Chiou, “Efficient design of low-complexity bit-parallel systolic Hankel multipliers to implement multiplication in normal and dual bases of GF(2m) ”, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science, Vol.E88-A, No.11, pp.3169-3179, Nov. 2005.
24. C.W. Chiou and C.Y. Lee, “Multiplexer-based double-exponentiation for normal basis of GF (2m) ”,Computers & Security, Vol.24, No.1, pp.83-86, 2005.
25. E. R. Berlekamp, “Bit-serial reed-solomon encoder”, IEEE Trans. Inform. Theory, Vol. IT-28, pp.869-874, Nov. 1982.
26. M. Morii, M. Kasahara, and D. L. Whiting, “Efficient bit-serial multiplication and the discrete-time Wiener-Hopf equation over finite fields”, IEEE Trans. Inform. Theory, Vol.35, No.6, pp.1177-1183, Nov. 1989.
27. H. Wu, M. A. Hasan, and I. F. Blake, “New low-complexity bit-parallel finite field multipliers using weakly dual bases”, IEEE Trans. Computers, Vol.47, No.11, pp.1223-1234, November 1998.
28. H. Wu and M. A. Hasan, “Low complexity bit-parallel multipliers for a class of finite fields”, IEEE Trans. Computers, Vol.47, No.8, pp.883-887, Aug. 1998.
29. S. T. J. Fenn, M. Benaissa, and D. Taylor, “ GF(2m) multiplication and division over the dual basis”, IEEE Trans. Computers, Vol.45, No.3, pp.319-327, March 1996.
30. C. C. Wang, “An algorithm to design finite field multipliers using a self-dual normal basis”, IEEE Trans. Computers, Vol.38, No.10, pp.1457-1459, Oct. 1989.
31. S. T. J. Fenn, M. Benaissa, and D. Taylor, “Dual basis systolic multipliers for GF(2m) ”, IEE Proc. Comput. Digit. Tech., Vol.144, No.1, pp.43-46, Jan. 1997.
32. M. Wang and I.F. Blake, “Bit serial multiplication in finite fields”, SIAM J. Disc. Math., Vol.3, No.1, pp.140-148, Feb. 1990.
33. M. Diab and A. Poli, “New bit-serial systolic multiplier for GF(2m) using irreducible trinomials”, Electronics Letters, Vol.27, No.13, pp.1183-1184, 1991.
34. J. Kelsey, B. Schneier, D. Wagner, and C. Hall, “Side-channel cryptanalysis of product ciphers”, Proc. of ESORICS, Springer, Sep.1998, pp.97-110.
35. E. Biham and A. Shamir, “Differential fault analysis of secret key cryptosystems”, Proc. of Crypto, Springer LNCS 1294, 1997, pp.513-525.
36. D. Boneh, R. DeMillo, and R. Lipton, “On the importance of checking cryptographic protocols for faults”, Proc. of Eurocrypt, Springer LNCS 1233, 1997, pp.37-51.
37. C.H. Chang, H.W. Chang, T.-L. Lee, T.L. Chen, C.W. Chiou, F.H. Chou, C.Y. Lee, “Concurrent error detection in advanced encryption standard (AES) ”, Proc. of the 17th International Conference on Information Management, Kao hsiung Country, Taiwan, pp.455-462,27 May, 2006.
38. Karri, R., Wu, K., Mishra, P., Kim, Y., “Fault-based side-channel cryptanalysis tolerant Rijndael symmetric block cipher architecture”, IEEE Int’l Symp Defect Fault Tolerance VLSI Syst , Page(s):427 – 435, Oct. 2001.
39. C.-Y. Lee, C.W. Chiou, J.-L. Lin, “Concurrent error detection in a bit-parallel systolic multiplier for dual basis of GF(2m) ”, Journal of Electronic Testing: Theory and Applications, Vol.21, No.5, 2005, pp.539-549.
40. C.W. Chiou, “Concurrent error detection in array multipliers for GF(2m) fields”, IEE Electronics Letters, Vol.38, No.14, 4th July 2002, pp.688-689.
41. C.-Y. Lee, C.W. Chiou, J.-L. Lin, “Concurrent error detection in a polynomial basis multiplier over GF(2m) ”, Journal of Electronic Testing: Theory and Applications, Vol.22, No.2, pp.143-150, April 2006.
42. C.W. Chiou, C.-Y. Lee, A.W. Deng, and J.-M. Lin, “Concurrent error detection in montgomery multiplication over GF(2m) ”, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science, Vol.E89-A, No.2, pp.566-574, Feb. 2006.
43. J. H. Patel and L.Y. Fung, “Concurrent error detection in ALU’s by recomputing with shifted operands”, IEEE Trans. Computers, Vol.C-31, No.7, July 1982, pp.589-595.
44. J.H. Patel and L.Y. Fung, “Concurrent error detection in multiply and divide arrays”, IEEE Trans. Computers, Vol.C-32, No.4, April 1983, pp.417-422.
45. R.H. Minero, A.J. Anello, R.G. Furey, and L.R. Palounek, “Checking by pseuduplication”, U.S. Patent 3660646, May 1972
46. H.S Kim and S.W. Lee, “Low complexity systolic architecture for modular multiplication over GF(2m) ”, Proc. of ICCS 2006, Part I, May 2006, pp. 634- 640.
47. C.S.Yeh, S.Reed, and T.K.Truong, “Systolic multipliers for finite fields GF(2m) ”, IEEE Trans. Computer, vol.C-33, Apr. 1984, pp.357-360.
48. C.L.Wang and J.L.Lin, “Systolic array implementation of multipliers for finite fields GF(2m) ”, IEEE Trans. Circuits and Systems, vol.38, July 1991, pp796-800.
49. S.K. Jain, L. Song and K.K. Parehi, “Efficient semisystolic architectures for finite field Arithmetic”, IEEE Trans. on VLSI Systems, vol. 6, no. 1, Mar. 1998.
50. C.W. Wu and M.K. Chang, “Bit-level systolic arrays for finite-field multiplications”, Journal of VLSI Signal Processing, vol. 10, pp.85-92, 1995.
51. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A System Perspective, Reading, Mass.: Addison-Wesley, 1985
52. “M74HC86, Quad Exclusive OR Gate”, STMicroelectronics, 2001,
http://www.st.com/stonline/books/pdf/docs/2006.pdf.
53. “M74HC08, Quad 2-input AND Gate”, STMicroelectronics, 2001,
http://www.st.com/stonline/books/pdf/docs/1885.pdf.
54. “M74HC279, Quad - Latch”, STMicroelectronics, 2001,
http://www.st.com/stonline/books/pdf/docs/1937.pdf.
55. “M74HC32, Quad 2-input OR Gate”, STMicroelectronics, 2001,
http://www.st.com/stonline/books/pdf/docs/1944.pdf
56. “M74HC11, Triple 3-inpout AND Gate”, STMicroelectronics, 2001,
http://www.st.com/stonline/books/pdf/doce/1890.pdf
57. “M74AC1157, 2 to 1 Multiplexer ”, STMicroelectronics, 5144,
http://www.st.com/stonline/books/pdf/doce/5144.pdf
58. A. J. Menezes, Applications of finite fields, Boston: Kluwer Academic, 1993.
59. Wakerly John, Error detecting codes, self-checking circuits and applications, New York : North-Holland, 1981.
60. P.K. Lala, Fault tolerant & fault testable hardware design, Prentice-Hall International, Inc., London, 1985.
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