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研究生:張朝偉
研究生(外文):Chou-Wei Chang
論文名稱:電阻電容反相器之基底和閘級觸發N型金氧半場效電晶體靜電放電防護電路設計與分析
論文名稱(外文):DESIGN AND ANALYSIS OF RC-INVERTER-SUBSTRATE AND GATE TRIGGERING NMOS ESD PROTECTION CIRCUIT
指導教授:黃至堯
指導教授(外文):Chih-Yao Huang
學位類別:碩士
校院名稱:清雲科技大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:94
語文別:英文
論文頁數:95
中文關鍵詞:靜電放電閘極耦合基底及閘極觸發電性過壓二次崩潰點電流
外文關鍵詞:ESDGate-couplingsubstrate and gate triggeringover-drivingsecond breakdown current
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閘極接地的N型金氧半場效電晶體通常使用於靜電放電保護元件,可是其電流不均勻分布的問題會降低靜電放電防護效能,閘極耦合技術藉由增加閘極電壓及降低第一次崩潰點電壓促使放電電流均勻分布。因為閘極耦合方式有閘極過壓問題之弱點,所以提出基底和閘級觸發方式以克服閘極過壓的問題,基底和閘級觸發結構除了改善閘極過壓問題之外,其佈局面積相較於閘極耦合方式只需三分之一,接著我們更進一步研究利用電阻電容反向器之金氧半電路來分辨靜電放電脈衝以及驅動N型金氧半靜電元件,電阻電容反相器之基底和閘級觸發N型金氧半電路之二次崩潰點電流為2.95安培,相較於閘極接地的N型金氧半電路改善了約58%,相較於電阻電容反相器之閘極耦合以及電阻電容之閘極耦合電路,電阻電容反相器之基底和閘級觸發N型金氧半電路有更快的閘極電壓反應速度、更高的二次崩潰點電流以及避免了閘極過壓問題。
Grounded-gate NMOS devices are commonly used for ESD protection but its non-uniform current distribution problem will reduce its ESD performance. Gate-coupling technique that increases the gate bias and reduces the voltage of first trigger point enables uniform ESD current distribution. Because the gate-coupling style still has its weakness of gate over-driving problem. A substrate-and-gate-triggering style is proposed to overcome the over-driving problem. Substrate-and-gate-triggering structure not only improve the over-driving problem, its layout area consumption is only 1/3 smaller than that of gate-coupling technique. we further investigates an ESD detection circuit which uses an RC inverter with a MOS structure to distinguish the ESD pulse and drives this NMOS clamping device. The second breakdown current of the RC-inv-SGTNMOS is 2.95A which is almost 58% improvement from the GGNMOS case. As compared with the RC-inv-GCNMOS and RC-GCNMOS styles, the RC-inv-SGTNMOS has faster drain voltage response time and also a higher second breakdown current value without gate over-driving effect.
Abstract(Chinese)……………………………………………………………………… i
Abstract(English)……………………………………………………….……………… ii
誌謝………………………………………………………………………………………... iii
Content…………………………………………………………………………………….. iv
Table List………………………………………………………………………………….. vi
Figure Captions……………………………………………………………………………. vii
Chapter1 INTRODUCTION………………………………………………………………. 1
1.1 Background…………………………………………………………………... 1
1.2 The ESD Problem……………………………………………………………. 2
   1.3 A Background of ESD Protection……………………………………………. 3
1.4 Thesis Organization………………………………………………………….. 4
Chapter2 ESD STRESS MODELS, TEST STANDARDS AND ESD PROTECTION
DEVICES……………………………………………………………………….. 6
2.1 The ESD Models……………………………………………………………... 6
2.1.1 Human Body Model(HBM)………………………………………….. 7
2.1.2 Machine Model(MM)………………………………………………… 9
2.1.3 Charged-Device Model(CDM)………………………………………… 10
2.1.4 Field Induced Charged Device Model (FIM / FCDM)…………………. 11
2.2 ESD Protection Devices……………………………………………………… 11
2.2.1 Diffusion or poly resistor………………………………………………... 12
2.2.2 P-N Junction Diode…………………………………………………….... 14
2.2.3 Bipolar Junction Transistor (BJT)………………………………….…… 15
2.2.4 MOS Transistor…………………….…………………………………… 18
Chapter 3 DESIGN OF GATE-COUPLED AND SUBSTRATE-GATE-TRIGGERING NMOS PROTECTION DEVICE……………………………………………… 22
3.1 Motive………………………………………………………………………. 22
3.2 Quasi Three Dimensional Simulation Scheme……………………………… 23
3.3 Simulation Result and Analysis of the resistance Gate-Coupled NMOS and Substrate-Gate-Triggering NMOS device…………………………………… 27
3.4 Simulation Result and Analysis for RC Time Control Circuit………….…. 35

3.5 Layout design for Gate-coupled NMOS and Substrate-gate-triggered NMOS device…………………………………………………………………………

36
Chapter 4 DESIGN AND ANALYSIS OF RC-INVERTER-SUBSTRATE AND GATE TRIGGERING NMOS PROTECTION DEVICE……………………………… 53
4.1 Motivation…………………………………..…………………………….. 53
4.2 RC-inverter-Substrate-and-Gate-Triggering Nmos Scheme……………… 54
4.3 Simulation Result and Analysis of RC-Inverter-Substrate-and-Gate-
Triggering NMOS protection device…………………………………………. 60
4.4 Layout design for RC-Inverter-Gate-Coupled NMOS……………….……... 75
Chapter 5 CONCLUSIONS……………………………………………………………...... 76
5.1 Conclusion…………………………………………………………………. 76
5.2 Future work………………………………………………………………... 77
Reference…………………………………………………………………………………... 78
簡歷………………………………………………………………………………………... 81
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