臺灣博碩士論文加值系統

目前使用FPGA實現可程式化晶片系統System on Programmable Chip(SoPC)受到大家相當的重視，除了系統本身就是嵌入式系統(Embedded System)與FPGA的結合外，更具有特定IC(Application Specific Integrated Circuit, ASIC)設計所欠缺的”可重組性” (Reconfiguration)，也因此可重組性的特點使得FPGA的運用有必要深入的加以研究。本篇論文即是利用FPGA的特性，深入研究其部分可重組性(Partial Reconfiguration)及自我重組(Self-Reconfiguration)的技術，進而發展出需求時自我重組系統(On-Demand Self-Reconfiguration System , ODSR System)，利用該系統部分重組的技術不僅可重複執行多種不同應用程式而因此減少FPGA邏輯閘的使用量，隨著部分重組技術的提升，FPGA的耗電量及面積可以大幅的減少。
本論文另外提出應用需求時自我重組系統配合Xilkernel軟體機制的一種新型態協同處理 (Coprocessing)設計方法。在實驗中，利用該設計方法，將影像處理常用的反離散餘弦轉換(Inverse Discrete Cosine Transform)與離散餘弦轉換(Discrete Cosine Transform)實做成協同處理型態的硬體線路，並配合特殊的Bus Macro匯流排將協同處理電路與MicroBlaze做連結溝通，而且將部分重組資料流(Partial Bitstream)儲存於外部的CompactFlash儲存體內，當需要做自我重組行為時即可由該儲存媒體內，找出所需部分重組資料流，同時燒錄電路至FPGA，最後將此架構以JPEG壓縮系統為例，在效率及硬體資源方面做一個完整的實驗得到相對的一些數據，說明ODSR System在支援影像處理的應用上是可行的。

Currently, there are many researches have paid much attention to SOPC (System on Programmable Chip). Not only SOPC integrates an embedded system into FPGA but also contains a “reconfiguration” feature which the design method of ASIC (Application Specific Integrated Circuit) lacks. Due to this property, FPGA can be applied beyond general expectations. This study investigated partial reconfiguration, self-reconfiguration and developed a hardware and a software mechanism to realize On-Demand Self-Reconfiguration (ODSR). Moreover, the ODSR system can dramatically reduce cost by partial reconfiguration and reduce the utilization of gate counts for multiple applications in one FPGA system. In addition, power consumption and gate area may be reduced according to saving gate counts.
For this thesis describes a novel method to achieve a coprocessing task use the self-reconfiguration technology and the specific software mechanisms by Xilkernel. In a practical experiment, we used Inverse Discrete Cosine Transform (iDCT) and Discrete Cosine Transform (DCT) hardware circuits to the coprocessing, and a Fast Simplex Link (FSL) bus as a linking connects on task of the coprocessing circuit and the MicroBlaze using specific bus - Bus Macro. In addition, the coprocessing tasks were transformed to the partial bitstreams stored in a CompactFlash storage, can be downloaded into FPGA on demand. At last, the experimental results of JPEG Compression Sytem demonstrate that the ODSR System is efficient enough for some specific Image Processing System.

第一章 緒論
1.1 研究動機
1.2 研究目的
1.3 論文架構
第二章 相關技術背景
2.1 FPGA概述
2.2 部分重組系統Partial Reconfiguration
2.2.1 Module Based
2.2.2 模組化設計流程
2.2.3 Difference Based
2.3 FPGA重組介面(Configuration Interface)
2.3.1 Configuration of Virtex FPGAs Boundary Scan (JTAG)
2.3.2 SelectMAP架構
2.4 System on Programmable Chip (SOPC)
2.4.1 SOPC概述
2.4.2 Xilinx Platform Studio設計流程
2.5 重組資料流(Bitstream)格式
第三章 需求時自我重組系統 (ODSR System)
3.1 ODSR系統架構雛形
3.2 協同處理器Coprocessor
3.3 硬體架構
3.3.1 MicroBlaze
3.3.2 Internal Configuration Access Port (ICAP)介面
3.3.3 Bus Macro Communication
3.4 軟體架構
第四章 設計流程詳述
4.1 Partial Reconfiguration 設計實務
4.1.1 Partial Reconfiguration注意事項
4.1.2 Partial Reconfiguration設計流程
4.2 MicroBlaze模組化與Self-Reconfiguration設計實務
第五章 實作影像處理與實驗結果
5.1 JPEG壓縮技術
5.2 離散餘弦轉換
5.3 JPEG壓縮程式實現於MicroBlaze平台
第六章 結論與未來研究方向
6.1 結論
6.2 未來研究方向--多區塊(Multi-Block )部分重組
參考文獻
附 錄
附錄一 Top-Level VHDL Design
附錄二 Modular MicroBlaze UCF

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