臺灣博碩士論文加值系統

對數數字系統算術是很有效率的，此為對於某些複雜函數而言。然而對數加法和對數減法的硬體成本大，造成實現上有成本考量的問題。動態部份重組系統能依需求的改變，於系統執行期間動態載入或移除FPGA的硬體規劃。本論文以動態部分可重組式計算的技術方法，將FPGA中的浮點數算術單元動態地修改成對數算術單元，如此解決對數數字系統的大硬體成本的問題。移除算術單元的規劃亦能使得耗電量減少。單音語音辨認為論文的應用範例。將單音語音辨認的演算法分成軟硬體兩部分，軟體部分於微處理器上執行，硬體部分則為自訂的對數和浮點數算術單元。動態部份重組系統硬體的設計流程採用Xilinx模組化設計流程、修改過的EDK流程及自我可動態重組的方式，另外我們還額外加入除錯(Debug)元件，擴大原本流程的可應用範圍。採用Xilinx的多媒體Virtex2-2000板子。實驗結果為單音語音辨認的速度可加快，重組浮點數單元需要約0.35秒，重組浮點數算術單元為對數單元需要約0.47秒。

Logarithmic number system (LNS) arithmetic is very efficient for some complex functions. However, LNS arithmetic has the problem of large hardware cost for LNS addition and subtraction, which make its implementation become impractical. The dynamic partial reconfiguration system can load or remove the bit stream of FPGA programming in run time. By using dynamic reconfiguration method, we can dynamically modify the floating-point arithmetic unit to LNS arithmetic unit in the FPGA hardware. The large-hardware-cost problem of LNS arithmetic can thus be solved, and the power consumption of the arithmetic system can also be reduced. Single-word speech recognition is taken as a demonstration example for our dynamic reconfiguration approach. We divide the speech recognition system into hardware and software parts. The software part is executed by the Xilinx microblaze processor, while the hardware part is operated by the FPGA hardware with FLP or LNS arithmetic units. The design flow of our dynamic reconfiguration includes Xilinx module design flow, modified EDK design flow, and dynamic self-reconfigurable approach. Furthermore, we also add a debug module. Our experiments are implemented on the Xilinx multimedia board Virtex II-2000. Our experimental results show that LNS arithmetic unit can enhance the speed of the speech recognition, and the reconfiguration time for the 32-bit FLP unit is about 0.35 second, while the FLP unit takes about 0.47 second to reconfigure the LNS unit.

誌謝 i
中文摘要 ii
Abstract iii
目錄 iv
圖目錄 vi
表目錄 vii
第一章 導論 1
1.1研究背景 1
1.2研究動機 2
1.3研究目的與工作 2
1.4論文架構 3
第二章 浮點數數字系統 5
2.1 IEEE 浮點數數字系統標準格式及其可表示的範圍與精準度 5
2.2 浮點數加減法演算法 6
2.3 浮點數乘法演算法 7
2.4 浮點數除法演算法及高效率除法演算法 8
2.5 浮點數算術單元電路設計及驅動程式 9
第三章 對數數字系統 12
3.1對數數字系統格式及其可表示的範圍與精準度 12
3.2對數數字系統之四則運算 13
3.3對數算術單元電路設計及驅動程式 14
第四章 語音辨識 18
4.1語音辨識流程 18
4.2擷取語音的特徵值 20
4.3訓練語音隱藏式馬可夫模型 24
4.4語音辨識中用硬體算術單元計算之函數 27
第五章 Xilinx SOPC發展環境 29
5.1 前言 29
5.2 Microblaze軟式處理器 29
5.3 Xilinx FPGA架構 30
5.4 Xilinx SOPC開發流程 32
5.5 Profile介紹 34
第六章 Xilinx可重組式計算 36
6.1 文獻研討 36
6.2 可重組式計算原理 41
6.3 Xilinx可重組式計算 41
6.4動態可重組式計算系統設計流程 45
第七章 實驗方法與結果 50
7.1語音辨識實驗環境與結果 50
7.2動態部分重組實驗方法與結果 52
第八章 結論 56
附錄A 動態可部份重組系統的設計流程 61

[1] Katherine Compton, ”Reconfigurable Computing: A Survey of Systems and Software”, ACM Survey, June 2002
[2] G. L. Sicuranza, “On efficient implementations of 2-D digital filters using logarithmic number system,” IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-31, pp. 877-885, 1983.
[3] E. E. Swartzlander Jr., D. V. S. Chandra, H. T. Nagle Jr., and S. A. Starks, "Sign/logarithm arithmetic for FFT implementation," IEEE Transactions on Computers, vol. C-32, pp. 526-534, June 1983.
[4] Debasish Das, Krishnendu Mukhopadhyaya, and Bhabani P. Sinha, “Implementation of four common functions on an LNS co-processor,” IEEE Transaction on Computers, vol. 44, no. 1, pp. 155-161, Jan. 1995.
[5] T. Stouraitis and V. Paliouras, “Considering the alternatives in low-power design,” IEEE Circuits and Devices Magazine, July 2001, pp. 23-29.
[6] Israel Koren, Computer Arithmetic Algorithms, New Jersey: Prentice-Hall, Inc., chapter 4, pp.45-70, 1993.
[7] Albert A. Liddicoat and Michael J. Flynn, “High-Performance Floating Point Divide,” Proc. Euromicro Symposium on Digital Systems, pp. 354-361, 2001.
[8] M. L. Frey and F. J. Taylor, “A table reduction technique for logarithmically architected digital filters,” IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. ASSP-33, no. 3, pp. 718-719, June 1985.
[9] David M. Lewis, “An architecture for addition and subtraction of long word length numbers in the logarithmic number system,” IEEE Transactions on Computers, vol. 39, no. 11, pp. 1325-1336, Nov. 1990.
[10] Lawrence K. Yu and David M. Lewis, “A 30-b integrated logarithmic number system processor," IEEE Journal of Solid-State Circuits, vol. 26, pp. 1433-1440, Oct. 1991.
[11] David M. Lewis, “Interleaved memory function interpolators with applications to an accurate LNS arithmetic unit,” IEEE Transactions on Computers, vol. 43, no. 8, pp. 974-982, Aug. 1994.
[12] Hartmut Henkel, “Improved addition for logarithmic number system,” IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. 37, no. 2, pp. 301-303, Feb. 1989.
[13] J. N. Coleman and E. I. Chester, “A 32-bit logarithmic arithmetic unit and its performance compared to floating-point,” Proceedings of 14th IEEE Symposium on Computer Arithmetic, Australia, pp. 142-151, 1999.
[14] Mark G. Arnold, Thomas A. Bailey, John R. Cowles, and Jerry J. Cupal, “Redundant logarithmic arithmetic," IEEE Transactions on Computers, vol. 39, pp. 1077-1086, Aug. 1990.
[15] Jean-Michel Muller, Alexandre Scherbyna, and Arnaud Tisserand, “Semi-Logarithmic number systems,” IEEE Transactions on Computers, vol. 47, no. 2, pp. 145-151, Feb. 1998.
[16] Fang-shi Lai and Ching-Farn Eric Wu, “A hybrid number system processor with geometric and complex arithmetic capabilities,” IEEE Transactions on Computers, vol. 40, no. 8, pp. 952-962, Aug. 1991.
[18] 顏敏男，“Design of A 32-bit Multi-Function LNS Arithmetic Unit on An SOPC System And Its Applications,” 逢甲大學資訊工程學系，2005。
[19] J. –A. Pineiro, M. D. Ercegovac, J. D. Bruguera, “High-radix logarithm with selection by rounding,” Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP’02), 2002, pp. 101-110.
[20] Chichyang Chen, Rui-Lin Chen, “A hardware algorithm for fast logarithmic computation”, submitted to Journal of the Chinese Institute of Engineer, 2003.
[21] J. F. Hart et al., Computer Approximations. New York: John Wiley & Sons, 1968.
[22] I. Koren and O. Zinaty, “Evaluating elementary functions in a numerical co-processor based on rational approximations,” IEEE Transactions on Computers, vol. 39, no. 8, pp. 1030-1037, Aug. 1990.
[23] Vitit kantabutra, “On hardware for computing exponential and trigonometric functions,” IEEE Transactions on Computers, vol. 45, no. 3, March 1996.
[24] Xilinx Guide, ”The Modular Design chapters of the Xilinx Development Systems Reference Guide”, “Synthesis and Simulation Design Guide”, “XST User Guide”.
[25] Xilinx Application Note 290, ”Two Flows for Partial Reconfiguration: Module Based or Difference Based”, 9 September 2004.
[26] Gregory Mermoud, ”A Module-Based Dynamic Partial Reconfiguration tutorial”, 1 November 2004.
[27] Xilinx Guide UG208, “Early Access Partial Reconfiguration User Guide”, March 6, 2006.
[28] Xilinx Data Sheet 280, OPB HWICAP, 15 March 2004
[29] “Modular dynamic reconfiguration in Virtex FPGAs,” IEE Process –Computer Digitial. Tech. May, 2006
[30] 沈�琤矷A“Implementation of Speech Recognition with Floating-Point and LNS Arithmetic in SOPC System,” 逢甲大學資訊工程學系，2005。
[31] 廖建誠，“語音辨識硬體設計於Xilinx可重組之單晶片系統”，逢甲大學碩士論文，2006。
[32] 廖千毅，“實現於可重組式單晶片系統之語音辨識系統的效能改善”，逢甲大學碩士論文，2005。
[33] “MicroBlaze Processor Reference Guide”, 2005.
[34] ”Virtex-II Platform FPGAs : Complete Data Sheet”.
[35] Chichyang Chen, Rui-Lin Chen, “A hardware algorithm for fast logarithmic computation”, submitted to Journal of the Chinese Institute of Engineer, 2003.
[36] Horta, E.L., and Lockwood, J.W., and Kofuji, S.: “Using PARBIT to implement partial run-time reconfigurable systems”, Field Programmable Logic and Applications, September 2002,(Springer Verlag), pp. 182-191.
[37] Guccione, S., Levi, D., and Sundararajan, P.: “JBits: Java based interface for reconfigurable computing”, Military and Aerospace Applications of Programmable Devices and Technologies Int. Confence, 1999.