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研究生:陳宣宇
研究生(外文):HsuanYu Chen
論文名稱:非中斷多執行緒結構的推測執行
論文名稱(外文):Speculative Execution of Non-Blocking Multithreaded Architecture
指導教授:周賜福周賜福引用關係
指導教授(外文):Joseph Arul
學位類別:碩士
校院名稱:輔仁大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:英文
論文頁數:74
中文關鍵詞:推測執行非中斷執行緒可排程資料流架構
外文關鍵詞:speculative executionnon-blocking multithreadSDF
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指令階層平行(ILP)技術在現今計算機組織與結構上已被廣泛使用,在控制流電腦架構上的發展也非常的成熟;因此這份研究在探討另一種電腦架構的運用結果,我們選擇在資料流(data flow)電腦結構下,應用指令階層平行中,經常使用到的技術-推測(Speculation)。在多執行緒已排班的資料流架構(SDF)上,使用非中斷多執行緒(non-blocking multithreaded)及退耦式(decoupled)的記憶體存取模式。而推測是一種根據指令集特性來進行“猜”的動作,並且在指令、資料或控制相依性高造成讓處理器等待(stall)的情況下,搬動其他非相依性的指令跨越到猜測指令或其他相依性的指令,便可有效利用管線化(pipeline)中的時脈週期(clock cycles)來進行其他指令執行,而具有分支預測(branch prediction)的動態排程(dynamic scheduling)便稱之為推測執行(speculation execution)。研究最後我們測試了幾個具代表性的程式來評估,觀察單位週期指令數(CPI)及單位指令週期數(IPC)的情形,實驗結果顯示利用推測執行在資料流電腦結構上確實可達到更好的運用效果。
In the past decade, CPU speed has been increasing linearly, but the memory access has not kept up with this improvement. In the modern architectures if we want to increase the processor performance, we need to increase the ILP. TLP has been complemented to ILP, in multithreaded architectures. In this thesis, we present an evaluation of modern processor that decouples memory accesses to alleviate the gap, uses a non-blocking multithreaded together with the dataflow paradigm. We provide both clock cycles per instruction (CPI) and instructions per clock cycle (IPC) evaluation of a multithreaded architecture by using speculative execution. Current architectural paradigm shift is from high performance to high-throughput processing, using on chip processors or by using distributed components. Main reasons to experiment speculative execution is by the witnessing of the diminishing potential of the existing techniques to extract parallelism from single program and current technology trends that allow us to execute multiple independent threads. The existing architecture has been evaluated previously and shown that it has outperformed MIPS like architectures. In this particular study, we try to implement speculative execution of a multithread on this unique architecture. We have used hand coded examples for speculative and non-speculative execution. Using few benchmarks, we present the IPC and CPI improvement over non-speculative execution. Some of the benchmarks we used include I-structure that is unique to dataflow architecture and other benchmarks are without I-structure. All the benchmarks have shown speedup of about 1.3. Without speculation we can only divide the programs conservatively into non-speculative threads, whose mutual exclusion and independence is guaranteed. In a speculative execution, it divides the thread aggressively and the mutual exclusion and dependence are guaranteed to be parallel. Thus it can increase the performance of any program with high probability. That has been proved as a result of this research using in a non-blocking multithreaded architecture. We have used different architectural simulators to prove the existing performance improvement of speculative execution.
摘要
Abstract
Chapter 1 Introduction
1.1 Motivation
1.2 Organization of This Thesis
Chapter 2 Background and Related Research
2.1 Background
2.2 Related Researches
Chapter 3 Speculative Execution
3.1 The Speculative execution and the Modern Microprocessors
3.2 Speculative Execution on Multithreaded Processors
3.2.1 Non-speculative Control-driven VS. Speculative Control-driven
3.2.2 Non-speculative Data-driven VS. Speculative Data-driven
3.3 Speculative Execution on a Non-blocking Multithreaded Architecture
Chapter 4 Non-blocking Multithreaded Architecture
4.1 Scheduled Data Flow (SDF) Architecture Overview
4.1.1 Non-blocking Thread Structure
4.1.2 Execution and Synchronization Pipeline
4.2 Non-speculative Execution in SDF
4.3 Speculative Execution in SDF
4.3.1 Extension of Instruction Set and the Thread Structure
4.3.2 Iteration in Speculative Execution
Chapter 5 Speculative VS. Non-speculative Benchmark Evaluation
5.1 Benchmarks Used
5.2 Programs without I-structure Usage
5.3 Programs with I-Structure Usage
5.4 Analysis of the CPI Improvement
Chapter 6 Conclusions
Reference
[1] K.M. Kavi, H.S. Kim, and A.R. Hurson, “Scheduled Dataflow Architecture: A Synchronous Execution Paradigm for Dataflow,” IASTED J. and Applications.Vol.21, no. 3, pp.114-124, Oct. 1999.

[2] K.M. Kavi, J.M. Arul and R.M. Giorgi, “Execution and Cache Performance of the Scheduled Dataflow Architecture,” J.Universal Computer Science, special issue on multithreaded and chip multiprocessors, vol. 6, no.10, pp.948-967, Oct. 2000.

[3] K.M. Kavi, R.M. Giorgi, J.M. Arul, “Scheduled Dataflow: Execution Paradigm, Architecture, and Performance Evaluation,” IEEE Trans. On Computers, Vol. 50, No. 8, pp.834-846, August 2001.

[4] J.M. Arul, Tsozeh Yeh, Chiacheng Hsu, Janjr Li, “ An Efficient Way of Passing of Data in a Multithreaded Scheduled Dataflow Architecture,” Proc. 8th International Conference on High-Performance Computing in Asia-Pacific Region, pp.487-492, Dec. 2005.

[5] Huiyang Zhou, Chao-Ying Fu, Eric Rotenberg, Thomas M. Conte,“A Study of Value Speculative Execution and Misspeculation Recovery in Superscalar Microprocessors,” Department of Electric & Computer Engineering, North Carolina State University, pp.--23.

[6] Arturo González-Escribano, Diego R. Llanos. “Speculative Parallelization,” ISSN 0018-9162, IEEE Press On Computer, vol. 39, no. 12, pp. 126-128, December 2006.

[7] Won W. Ro, Jean-Luc Gaudiot, “Compiler Support for Dynamic Speculative Pre-Execution,” Proceedings of the Seventh Workshop on Interaction between Compilers and Computer Architectures, p.14, February 08-08, 2003.

[8] Marcuello, Pedro Antonio Gonzalez, “Data Speculative Multithreaded Architecture,” 24th Euromicro Conference Proceedings, IEEE 1998, vol. 1, pp. 321-324.

[9] Jim Pierce, Trevor N. Mudge,“The Effect of Speculative Execution on Cache Performance,” Proceedings of the 8th International Symposium on Parallel Processing, p.172-179, April 01, 1994.

[10] Roberto Cordone, Fabrizio Ferrandi, Gianluca Palermo, Marco Domenico Santambrogio, Donatella Sciuto, “Using Speculative Computation and Parallelizing Techniques to Improve Scheduling of Control based Designs,” The 11th Asia and South Pacific Design Automation Conference Technical Program, IEEE 2006, pp 898-904.

[11] F. Chang and G. A. Gibson, “Automatic I/O Hint Generation Through Speculative Execution,” Proceedings of the USENIX Symposium on Operating Systems Design and Implementation (OSDI), New Orleans, LA, February 1999, pp. 1-14.

[12] G. Sohi and A. Roth, “Speculative Multithreaded Processors,” IEEE Computer 34, 4 (2001), 66-73.

[13] V. Krishnan and J. Torrellas,“Chip-Multiprocessor Architecture with Speculative Multithreading,”IEEE Trans. Computers, vol. 48, no.9, pp.886-880, Sept.1999.

[14] J.E SMITH, “Decoupled access/execute computer architectures,” Proceedings of the 9th annual symposium on Computer Architecture, p.112- 119, April, 1982.

[15] Gonzales, J., and Gonzalez, A., “Speculative Execution via Address Prediction and Data Prefetching,” Proc. of International Conference on Supercomputing 1997, ACM, NY, pp. 196-203 (1997).

[16] Pedro Marcuello , Jordi Tubella , Antonio González, “Value prediction for speculative multithreaded architectures,” Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture, p.230-236, November 16-18, 1999, Haifa, Israel.
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