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研究生:謝祥界
研究生(外文):HSIEH. HSIANG CHIEH
論文名稱:無線區域網路CMOS低雜訊放大器和發射接收切換開關器之設計
論文名稱(外文):802.11 WLAN CMOS LNA and T/R Switch Design
指導教授:林昇洲
指導教授(外文):Sheng-Chou Lin
學位類別:碩士
校院名稱:輔仁大學
系所名稱:電子工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:中文
論文頁數:66
中文關鍵詞:無線區域網路低雜訊放大器發射接收切換開關器
外文關鍵詞:WLANLNAT/R Switch
相關次數:
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  • 下載下載:100
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在無線通訊系統中,射頻前端電路也逐漸使用製作成本低與系統整合性高的CMOS 製程製作。本論文中,採用TSMC 0.18um所提供Model來設計無線區域網路5.2G Hz最簡化疊接式(cascode)低雜訊放大器電路,電路模擬結果可提供12.67dB 的增益、2.4dB 的雜訊指數、S11為-14.83dB、S22為-14.30dB、S12為-28.34dB、P1-dB為-13dB、IIP3為3.4dB及21.45mW 的功率消耗。而發射接收切換開關電路(T/R Switch) 設計在無線區域網路802.11ag 全頻帶,電路模擬結果可提供插入損失在2.45GHz為1.07dB 和5.45GHz為1.34dB、收發端隔離度在2.45GHz為48.02dB 和5.45GHz為41.33dB、天線與收發端隔離度在2.45GHz為46.56dB 和5.45GHz為39.85dB、天線端返回損耗在2.45GHz為-21.47dB 和5.45GHz為-17.39dB、P1-dB為12dB、收發端返回損耗在2.45GHz為-21.42dB 和5.45GHz為-17.43dB。
The low-noise amplifier became the quite important implementation of front-end circuit in communicate system, that’s because the signal transmitted from antenna and amplified through the low-noise amplifier immediately. Besides, the noise amplifier controls the whole radio’s noise figure and input VSWR. Therefore, The work use tsmc 0.18um 1P6M CMOS technology to develop 5GHz U-NII band 5.15~5.35GHZ CMOS LNA for the 802.11a WLAN. Simulate tool use Agilent EEsofe ADS, the simulated and noise figure was 2.4dB, the power gain was 12.67dB, the S11 was –14.83dB, the S22 was –14.30dB, the S12 was –28.34dB , the P1-dB was –13dB, the IIP3 was 3.4 dB, the power dissipation 21.45 mW. The work use tsmc 0.18um 1P6M CMOS technology to develop CMOS T/R switch for the 802.11ag WLAN. Simulate tool use Agilent EEsofe ADS the simulated insertion loss was 1.07dB at 2.45 GHz and 1.34 dB at 5.45 GHz, the between TX and RX port isolation was 48.02dB at 2.45 GHz and 41.33 dB at 5.45 GHz, the between antenna and TX (RX) port isolation was 46.56dB at 2.45 GHz and 39.85 GHz at 5.45 GHz, the antenna port return loss was –21.47dB at 2.45GHz and –17.39 dB at 5.45 GHz, the P1dB was 12 dB , the TX or RX port return loss was -21.42 dB at 2.45 GHz and –17.43 dB at 5.45 GHz.
中文摘要 i
英文摘要 ii
誌謝 iii
目錄 iv
表目錄 vii
圖目錄 viii
第一章 緒 論 1
1.1 研究動機 1
1.2 研究方法與目的 4
1.3 論文架構 5
第二章 理論分析 6
2.1 接收機架構 7
2.1.1超外差接收機(Super-Heterodyne Receiver)………………………....7
2.1.2直接降頻接收機架構(Direct-Conversion Receiver)…..............…......7
2.1.3雙降頻式超外差接收機(Double Down-Conversion Heterodyne Receiver)………………………………………………………...….10
2.2射頻電路設計考量 11
2.2.1雜訊 11
2.2.1.1 熱雜訊( Thermal noise )............................................................11
2.2.1.2 閃爍雜訊( Flicker noise )…......................................................13
2.2.1.3 電晶體的雜訊….......................................................................14
2.2.2雜訊指數 15
2.2.3非線性效應 17
2.2.3.1 諧波失真(Harmonic Distortion)…...........................................17
2.2.3.2 增益壓縮點(Gain compression)................................................18
2.2.3.3互調失真( Inter-Modulation Distortion; IMD )........................19
2.3 IEEE 802.11ag 之系統規格 21
2.3.1 RF 系統設計 23
2.3.2接收器系統模擬 25
2.4 S parameter(S 參數) 26
2.5穩定度的考量(Stability) 28
2.6 結論 29
第三章 低雜訊放大器設計 31
3.1低雜訊放大器簡介 31
3.2低雜訊放大器架構 31
3.3低雜訊放大器雜訊模型 34
3.4低雜訊放大器穩定性 37
3.5低雜訊放大器輸入端匹配 39
3.5.1電阻性終端( Resistive Termination ) 架構 39
3.5.2轉導終端 ( 1/gm Termination )架構 40
3.5.3並聯-串聯式回授( shunt-series feedback )架構 41
3.5.4電感退化性( Inductive degeneration )架構 42
3.6低雜訊放大器電路設計 43
3.7模擬實驗結果 44
3.7.1 DC Curve模擬 44
3.7.2 S參數模擬 45
3.7.3穩定度和雜訊指數模擬 47
3.7.4線性度模擬 47
3.7.5模擬結果比較 48
3.7.6結語 49
第四章 收發切換開關電路設計 50
4.1收發切換開關電路簡介 50
4.2收發切換開關電路規格 50
4.3電路架構原理 51
4.4收發切換開關種類 53
4.5高隔離度發射接收切換開關電路設計 54
4.5.1設計流程 54
4.5.2模擬結果 55
4.6 結論 60
第五章 結論 61
參考文獻 63
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