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研究生:江正雄
研究生(外文):Cheng-Hsiung Chiang
論文名稱:使用分離共平面在印刷電路板設計減少串音改善靜電放電耐受度
論文名稱(外文):Reducing Crosstalk for Improving Electrostatic Discharge Immunity Using Separated Common Plane in Printed Circuit Board Design
指導教授:李永勳
指導教授(外文):Yuang-Shung Lee
學位類別:碩士
校院名稱:輔仁大學
系所名稱:電子工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:中文
論文頁數:88
中文關鍵詞:靜電放電印刷電路板靜電放電產生器串音耐受度
外文關鍵詞:electrostatic discharge (ESD)printed circuit board (PCB)electrostatic discharge generatorcrosstalkimmunity
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目前電子設備及產品設計的趨勢是上升時間短、訊號速度快、電流需求更大、和更低的工作電壓,所以靜電放電對於產品設計人員變成日益嚴重的問題。本論文主要是針對如何在印刷電路板上改善靜電放電耐受度以加強產品可靠性。首先討論的是IEC61000-4-2所規範的靜電放電產生器,其放電電流波形在法規上的要求,再據此建立起靜電放電產生器的等效電路模型,並以數學方程式和實際量測驗證其準確性。然後利用此干擾源在不同的印刷電路板結構上作分析。正因為串音干擾是引起靜電放電導致產品功能受影響的主因之一,所以本文之研究針對降低串音干擾的方法上提出分離共平面的印刷電路板結構,同時在時域和頻域上作比較。最後,理論、模擬和量測數據得到一致結論。此方法至少具體以下幾個優點:1)較好的靜電放電耐受性和較低的串音干擾,2) 較少的印刷電路板幾何空間需求,3)無需額外元件增加成本即可達成。
The current trends of designing electronic equipments and products are short rise time, fast edge rate, high current requirement, and low voltage operation. Therefore, the electrostatic discharge (ESD) has become a more and more significant issue for product designer. This thesis mainly focuses on investigating how to improve ESD in a printed circuit board (PCB) in order to increase the reliability of electronic products. Firstly, the current waveform standard for the electrostatic discharge generator of IEC61000-4-2 is discussed. An equivalent ESD circuit is then established and its accuracy is confirmed through using mathematical equations and practical measurements. Afterward, this equivalent circuit model is applied as the electrostatic discharge source to further analyze various PCB trace structures. In general, crosstalk is one of the main factors causing ESD problems. This study tried to solve this problem by comparing the influences of crosstalk from different PCB trace structures in the time and frequency domains. Finally, from the results of this study, it can be found that the simulation results are in good agreement with the measurement results. Moreover, the results also show that separated common plane has the following major advantages for PCB design: 1) lower crosstalk with excellent ESD immunity; 2) smaller PCB layout spacing requirements; and 3) without the cost of adding additional component.
中文摘要………………………………………………………………………i
英文摘要………………………………………………………………………ii
誌謝……………………………………………………………………………iii
目錄……………………………………………………………………………iv
表目錄…………………………………………………………………………vii
圖目錄…………………………………………………………………………viii
符號說明………………………………………………………………………xii
第一章緒論……………………………………………………………………1
1.1 研究動機與目的…………………………………………………1
1.2 研究方法…………………………………………………………2
1.3 論文大綱…………………………………………………………3
第二章 印刷電路板微帶線結構串音原理分析……………………………4
2.1 簡介………………………………………………………………4
2.2 串音干擾之電磁場耦合…………………………………………5
2.3 串音干擾之電容性耦合…………………………………………8
2.4 串音干擾之電感性耦合…………………………………………11
2.5 串音干擾之共阻抗耦合…………………………………………14
2.6 減少串音干擾之對策研究………………………………………17
2.7 本章結論…………………………………………………………19
第三章 資訊產品靜電放電法規研究與其產生器模型分析設計…………20
3.1 簡介………………………………………………………………20
3.2 符合IEC 61000-4-2規範之靜電放電產生器…………………21
3.3 符合IEC 61000-4-2規範之測試配置與測試結果判定………27
3.4 靜電放電產生器電流波形之數學方程式研究…………………29
3.5 靜電放電產生器的等效電路模型設計與模擬…………………33
3.6 靜電放電產生器電流波形之實際量測…………………………35
3.7 本章結論…………………………………………………………39
第四章 印刷電路板之靜電放電串音模擬…………………………………40
4.1 簡介………………………………………………………………40
4.2 微帶線結構之串音現象在頻域上的模擬………………………40
4.3 微帶線結構之串音現象在時域上的模擬………………………49
4.4 微帶線與帶狀線結構的串音特性比較…………………………55
4.5 不同微帶線結構的靜電放電在串音上之模擬…………………60
4.6 不同微帶線結構的電磁場之比較………………………………68
4.7 本章結論…………………………………………………………72
第五章 實驗方法與量測結果………………………………………………73
5.1 簡介………………………………………………………………73
5.2 靜電放電的時域量測方法與實驗配置…………………………75
5.3 靜電放電的頻域量測方法與實驗配置…………………………77
5.4 不同靜電放電產生器之放電電流波形比較……………………78
5.5 本章結論…………………………………………………………80
第六章 結論與未來研究方向………………………………………………81
6.1 本論文之貢獻與結論……………………………………………81
6.2 未來研究方向……………………………………………………81
參考文獻………………………………………………………………………83
[1]GB/T 17626.2-1998電磁兼容試驗測量技術靜電放電抗擾度試驗, 中國標準出版社, 1996.6.
[2]SJ/T 10694-1996電子產品製造防靜電系統測試方法, 中華人民共和國電子工業部, 1997.
[3]GJB/Z 105-1998電子產品防靜電放電控制手冊, 國防科學技術工業委員會, 1998.
[4]M. D. Ker and S. H. Chen, “Implementation of Initial-On ESD Protection Concept with PMOS-Triggered SCR Devices in Deep-Submicron CMOS Technology,” IEEE J. Solid State Circuits, vol. 42, no. 5, pp. 1158-1168, May 2007.
[5]Y. Taur, “CMOS Design Near the Limit of Scaling,” IBMJ. Res. Develop., vol. 46, no. 2/3, pp. 213, 2002.
[6]Z. Chen, J. Appenzeller, Y. M. Lin, J. Sippel-Oakley, A. Rinzler, J. Tang, S. Wind, P. Solomon, and P. Avouris,“ An Integrated Logic Circuit Assembled on a Single Carbon Nanotube,” Science, vol. 311, no. 5768, pp. 1735, Mar. 2006.
[7]N. Mohan and A. Kumar, “Modeling ESD Protection,” IEEE Potentials, vol. 24, pp. 21-24, Feb.-Mar. 2005.
[8]W. T. Rhoades, “Avoidance of ESD effects,” IEEE Int. Symp. Electromagn. Compat., pp. 184-189, 1988.
[9]T. Sudo, H. Sasaki, N. Masuda, and J. L. Drewniak, “Electromagnetic Interference (EMI) of System-on-Package (SOP),” IEEE Trans. Adv. Packag., vol. 27, pp. 304-314, May 2004.
[10]A. Deutsch, G. V. Kopesay, P. J. Restle, H. Smith, G. Katopis, W. D. Becker, P. W. Coteus, C. W. Surovic, B. J. Rubin, R. P. Dunne, T. Gallo, K. A. Jenkins, L. M. Terman, R. H. Dennard, G. A. Sai-Halasz, and D. R. Knebel, “When are Transmission-Line Effects Important for On-Chip Interconnections?” IEEE Trans. Microwave Theory Tech., vol. 45, pp. 1836-1846, Oct. 1997.
[11]G. H. Shiue, S. M. Lin, and R. B. Wu, “Reduction in Reflections and Ground Bounce for Signal Line Through a Split Power Plane by Using Differential Coupled Microstrip Lines,” Proc. IEEE 12th Topical Meeting Elect. Performance Electron. Packag., pp. 107-110, 2003.
[12]H. Y. Shim, J. Kim, and J. G. Yook, “Modelling of ESD and EMI Problems in Split Multi-Layer Power Distribution Network,” IEEE Int. Symp. Electromagn. Compat., vol. 1, pp. 48-51, Aug. 2003.
[13]A. Suntives, A. Khajooeizadeh, and R. Abhari, “Using Via Fences for Crosstalk Reduction in PCB Circuits,” IEEE Int. Symp. Electromagnetic Compat., pp. 34-37, Aug. 2006.
[14]J. Zhang and Friedman. E. G., “Crosstalk Modeling for Coupled RLC Interconnects with Application to Shield Insertion,” IEEE Trans. Very Large Scale Integr.(VLSI) Syst., vol. 14, no. 6, pp. 641-646, Jun. 2006.
[15]Y. S. Sohn, J. C. Lee, H. J. Park, and S. I. Cho, “Empirical Equations on Electrical Parameters of Coupled Microstrip Lines for Crosstalk Estimation in Printed Circuit Board,” IEEE Trans. Adv. Packag., vol. 24, no. 4, pp. 521-527, Nov. 2001.
[16]Bruce Archambeault, PCB Design for Real-World EMI Control, Kluwer Academic, Chapter 2 and 10, 2002.
[17]IEC 61000-4-2, Electromagnetic compatibility (EMC) Part4: “Testing and Measurement Techniques-Section 2: Electrostatic Discharge Immunity Test,” 1995.
[18]J. S. Maas and D. J. Pratt, “A Study of the Repeatability of Electrostatic Discharge Simulators,” IEEE Int. Symp. Electromagn. Compat., pp. 265-269, Aug. 1990.
[19]D.D. Ward, “Electrostatic Discharge,” IEE Seminar on EMC Design, pp. 4/1-4/8, 1999.
[20]W. Rhoades and J. Maas, “New ANSI ESD Standard Overcoming the Deficiencies of Worldwide ESD Standards,” IEEE Int. Symp. Electromagn. Compat., vol. 2, pp. 1078-1082, Aug. 1998.
[21]K. Hall and D. McCarthy, “Tests with different IEC801.2 ESD Simulators Have Different Results Depending on Product Sensitivities,” IEEE Int. Symp. Electromagn. Compat., pp. 280-284, Aug. 1995.
[22]R. Chundru, D. Pommerenke, K. Wang, T. V. Doren, F. P. Centola, and J. S. Huang, “Characterization of Human Metal ESD Reference Discharge Event and Correlation of Generator Parameters to Failure Levels-Part I: Reference event,” IEEE Trans. Electromagn. Compat., vol. 46, no. 4, pp. 498-504, Nov. 2004.
[23]R. Chundru, D. Pommerenke, K. Wang, T. V. Doren, F. P. Centola, and J. S. Huang, “Characterization of Human Metal ESD Reference Discharge Event and Correlation of Generator Parameters to Failure Levels-Part II: Correlation of Generator Parameters to Failure Levels,” IEEE Trans. Electromagn. Compat., vol. 46, no. 4, pp. 505-511, Nov. 2004.
[24]Z. Yuan, J. He, R. Zeng, B, W. Chen, and S. Chen, “Transient Near-Field Effect of Electrostatic Discharge,” IEEE Trans on Magnetics., vol. 42, no. 4, pp. 795-798, April. 2006.
[25]D. C. Smith and M. Hogsett, “The EMI/ESD Environment of Large Server Installations,” EOS/ESD Symposium Proceedings, 2001.
[26]D. C. Smith and A. Wallash, “Electromagnetic Interference (EMI) Inside a Hard Disk Drive Due to External ESD,” EOS/ESD Symposium Proceedings, 2002.
[27]Advanced Design System (ADS), Agilent Technologies, http://eesof.tm.agilent.com/
[28]E. Bogatin, Signal Integrity- Simplified, Prentice Hall PTR, Chapter 10, 2004.
[29]B. Young, Digital Signal Integrity-Modeling and Simulation with Interconnects and Package, Prentice Hall PTR, Chapter 1, 2000.
[30]Stephen H. Hall, Garrett W. Hall and James A. McCall, High-Speed Digital System Design, John Wiley & Sons, Inc., Chapter 2, 2000.
[31]Bakoglu H., Circuit, Interconnections and Packaging for VLSI, Addison Wesley, Chapter 7, 1990.
[32]Y. S. Sohn, J. C. Lee, H. J. Park, S. I. Cho, “Empirical Equations on Electrical Parameters of Coupled Microstrip Lines for Crosstalk Estimation in Printed Circuit Board,” IEEE Trans. Adv. Packag., vol. 24, no. 4, pp. 521-527, Nov. 2001.
[33]H. Johnson and M. Graharm, High Speed Digital Design: A Handbook of Black Magic, Prentice, Chapter 5, 1993.
[34]C. R. Paul, Introduction to Electromagnetic Compatibility, 2nd edition, John Wiley & Sons, Inc., Chapter 9, 2006.
[35]T. M. Zeeff, T. H. Hubing, and T. P. V. Doren, “Traces in Proximity to Gaps in Return Planes,” IEEE Trans. Electromagn. Compat., vol. 47, no. 2, pp. 388-392, May 2005.
[36]“IEEE Standard Electrostatic Discharge Tests for Protective Relays,” IEEE Std, C37.90.3-2001, 2001.
[37]77B/538/CD, “IEC 61000-4-2: EMC-Part 4-2: Testing and Measurement Techniques - ESD Immunity Test”, Apr. 6, 2007.
[38]77B/378/CDV, “IEC 61000-4-2: EMC-Part 4-2: Testing and Measurement Techniques- ESD Immunity Test”, Apr. 11, 2003.
[39]W. Boxleitner, Electrostatic Discharge and Electronic Equipment: A Practical Guide for Designers to Prevent ESD Problem, IEEE press, New York, 1989.
[40]http://www.noiseken.com/english/equip/ess2002.htm.
[41]http://www.thermo.com/com/cda/product/detail/1,1055,18263,00.htm.
[42]http://www.emc-partner.com/pages/products.htm.
[43]G. P. Fotis, I. F. Gonos and I. A. Stathopulos, “Determination of Discharge Current Equation Parameters of ESD Using Genetic Algorithms,” Electronics Letters 6th, vol. 42, no. 14, pp. 797-799, July 2006.
[44]R. K. Keenan and L. A. Rosi, “Some Fundamental Aspects of ESD Testing,” IEEE Int. Symp. Electromagn. Compat., pp. 236-241, Aug. 1991.
[45]R. K. Keenan and L. A. Rosi, “Some Fundamental Aspects of ESD Testing, Part II,” IEEE Int. Symp. Electromagn. Compat., pp. 469-473, Aug. 1992.
[46]V. D. Berghe, Steve, and D. Zutter, Daniel, “ESD Entrypoints: Coaxial Cables vs. Shielding Aperures,” Electrical Overstress/Electrostatic Discharge Symposium Proceedings, Santa Clara, CA, pp. 76-82, Sept. 23-25, 1997.
[47]L. Shanghe, T. Zhiliang, X. Xiaoying, W. Guanghui, and W. Zhangcheng, “Study on ESD Characteristics and Its Effect Mechanism,” IEEE 2002 3rd Int. Symp. Electromagn. Compat., pp. 493-496, May 2002.
[48]K. Wang, D. Pommerenke, R. Chundru, T. V. Doren and J. L. Drewniak, “Numerical Modeling of Electrostatic Discharge Generators,” IEEE Trans Electromagn. Compat., vol. 45, no. 2, pp. 258-271, May 2003.
[49]Z. Yuan, T. Li, J. He, S. Chen, and R. Zeng, “New Mathematical Descriptions of ESD Current Waveform Based on the Polynomial of Pluse Function,” IEEE Trans. Electromagn. Compat., vol. 48, no. 3, pp. 589-591, Aug. 2006.
[50]“ABCs of Probes”, Tektronix Inc., 1997.
[51]Tektronix Inc., Beaverton, OR, “Tektronix logic analyzers,” (2006). [Online]. Available:http://www.Tektronix.com.
[52]S. Caniggia, and F. Maradei, “Circuit and Numerical Modeling of Electrostatic Discharge Generators,” IEEE Trans. on Industry Applications, vol. 42, no. 6, pp. 1350-1357, Nov. / Dec. 2006.
[53]F. Centola, D. Pommerenke, W. Kai, T. V. Doren and S. Caniggia, “ESD Excitation Model for Susceptibility Study,” IEEE Int. Symp. Electromagn. Compat., vol. 1, pp. 58-63, Aug. 2003.
[54]http://www.cadence.com/products/si_pk_bd/pcb_design/index.aspx.
[55]T. W. Kang, Y. C. Chung, S. H. Won, H. T. Kim, “On the Uncertainty in the Current Waveform Measurement of an ESD Generator,” IEEE Trans. Electromagn. Compat., vol. 42, no. 4, pp. 405-413, Nov. 2000.
[56]R. Xiaofen, Z. Xjun, W. Zhancheng, W. Shuping “Study on Two Types of Commercial ESD Simulators,” CEEM Proceedings, Asia-Pacific Conference on, pp. 233-236, 4-7 Nov. 2003.
[57]Z. Xijun, R. Xiaofen, L. Shanghe, W. Ming, “Study on the Effects of Relay Switch of ESD Simulator to ESD Immunity Test,” CEEM Proceedings, Asia-Pacific Conference on, pp. 229-232, Nov 4-7. 2003.
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