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研究生:郭肇勳
研究生(外文):Chao-Shun Kuo
論文名稱:利用現場可規劃邏輯陣列晶片設計一個高速的可程式直流電子負載控制系統
論文名稱(外文):Using an FPGA Chip to Design a High-speed Control System for Multiple Sets of Programmable DC Electronic Loads
指導教授:白英文白英文引用關係
指導教授(外文):Ying-Wen Bai
學位類別:碩士
校院名稱:輔仁大學
系所名稱:電子工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:中文
論文頁數:62
中文關鍵詞:動態控制系統可程式負載模式定負載模式動態負載模式
外文關鍵詞:DCSRun Program ModeConstant Load ModeDynamic Load Mode
相關次數:
  • 被引用被引用:5
  • 點閱點閱:325
  • 評分評分:
  • 下載下載:64
  • 收藏至我的研究室書目清單書目收藏:0
本論文主要的目的是設計一個高速的可程式直流電子負載的控制系統,將現場可規劃邏輯陣列晶片整合進可程式直流電子負載設計之中,作為微處理器控制單元的輔助處理器,使用超高速積體電路硬體描述語言(VHDL)設計一個新的動態控制系統(DCS)。利用可程式的設計與有效地記憶體的規劃,設計微處理器控制單元與現場可規劃邏輯陣列晶片之間的通訊介面,將週邊電路改以硬體的控制方式,取代以軟體控制的思維,增加電路設計的彈性,並減少微處理器控制單元資源的佔用,簡化軟體的設計流程,以增進整體效能。經由使用設計現場可規劃邏輯陣列晶片的開發工具模擬與驗證,並實際運用動態控制系統於可程式直流電子負載之中。動態控制系統在硬體處理速度快速與可同時輸出控制多個週邊電路的設計下,以精確的時序讓100組可程式測試參數設定值,在可程式負載模式資料流量大時,亦可達到每一筆資料傳輸的同步,並以分時的處理達到數個週邊電路控制上時序的要求,每組最短執行時間可達25uS。在使用定負載模式下,以定電流方式穩定拉載,且誤差可達1%以下,而在動態負載模式除了設定的執行時間準確外,切換頻率更可達20KHz。
The purpose of this paper is to design a high-speed control system for programmable DC electronic loads by combining an FPGA chip and a MCU (microcontroller unit). VHDL (Very High Speed Integrated Circuit Hardware Description Language) is used to devise a configurable control mechanism for a DCS (dynamic control system). Utilizing a programmable design and effective formulation in memory modules to design the commutation interface between MCU and FPGA chip, we replace the hardware design by the software controls of the peripheral circuits that add to the elasticity of the circuit design and lessen the resource demand by the MCU, to further simplify the procedure of the software design and to improve the design efficiency. By means of simulation and verification using the FPGA chip as our development tool we carry out experiments with the dynamic control system for programmable DC electronic loads. Our design provides the advantage of speeding the process of the hardware carrying out the concurrent output control for many peripheral circuits, allowing the setting of the programmable parameters of 100 sets to send out each datum synchronously when the Run Program Mode is in high data rate. This high data rate provides the timing demand of many peripheral circuits which are controlled by a time-sharing process. The shortest duration of each set reaches 25 µS, using our design which provides a constant current to sink stably under the Constant Load Mode with the error rate under 1%. The Dynamic Load Mode provides accuracy of duration, and switching frequency can reach 20 KHz.
中文摘要
英文摘要
誌謝
目錄
表目錄
圖目錄
符號說明
專有名詞表
一、 緒論
1.1 研究動機與背景
1.2 晶片的選擇與模擬環境
1.3 論文架構
二、 系統結構
2.1 可程式直流電子負載介紹
2.2 定電流模式
2.3 動態負載模式
2.4 系統的規劃
三、 現場可規劃邏輯陣列晶片設計與模擬
3.1 負載控制迴路
3.2 現場可規劃邏輯陣列晶片之EABs規劃
3.3 時序設計
3.4 功能模組的設計與模擬
3.5 DCS模擬與驗證
四、 實作結果與分析
4.1 數位訊號分析與驗證
4.2 實際功能操作與驗證分析
4.3 產品性能規格比較
五、 結論
5.1 整體系統成果
5.2 未來工作
參考文獻
附錄
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