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研究生:黃立威
研究生(外文):Li-wei Huang
論文名稱:使用二級ΔΣ調變器之6Gbit/s序列先進科技鏈接展頻時脈產生器
論文名稱(外文):A 6-Gbit/s SATA Spread-Spectrum Clock Generator Using Two-Stage Delta-Sigma Modulator
指導教授:呂學坤黃弘一
指導教授(外文):Shyue-Kung LuHong-Yi Huang
學位類別:碩士
校院名稱:輔仁大學
系所名稱:電子工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:英文
論文頁數:71
中文關鍵詞:展頻時脈產生器序列先進科技鏈接
外文關鍵詞:Spread-Spectrum Clock GeneratorSATA
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在資訊快速發展的電腦與網路社會,電子產品已成為我們生活不可或缺的必須品。操作速度越來越快的產品也越來越多,導致電磁干擾效應已成為我們目前研究之主要課題。不只是因為要考慮訊號間的完整性,而且更須重視其對人體健康之影響。因為較高之功率頻譜有可能危害我們的健康。
然而,高速電路在現今環境似乎是不可避免的。而其所產生之功率頻譜也較高,使得降低電磁干擾效應之困難度增加。許多降低電磁干擾的方法已經被提出。包括有訊號遮蔽、鎖相迴路輸出時脈調變…等。這將在未來電路設計上扮演重要角色。
序列資料傳輸裝置通常是使用在電腦資料中的硬碟裝置。它也有許多降低電磁干擾之規定,以避免其對於人體之影響。本論文將提出一個新架構之展頻時脈產生器,並可達到1.5-Gbit/s 、3-Gbit/s 及6-Gbit/s 之展頻規格。其中使用二個
ΔΣ調變器,可克服改善震盪器壓控電壓三角波調變之非線性,並簡化ΔΣ調變器設計之複雜度。此電路是由臺灣積體電路之0.18微米製程製造。其於6-GHz可降低功率頻譜17db。晶片尺寸為0.570.45 mm2 並操作於1.8-V 之供應電壓。
With rapid growth of the information in the computer and network society, there is no lack of electric products in our life. For more and more electric products which have higher and higher operate speed, the electromagnetic interference becomes the major topic between us. Not only for the considerations of signals integrity but also for the health of body. The higher power spectrum in certain frequency may be hazardous to our health.
The SATA device is used in computer’s data storage which called the hard disk. It also required the electromagnetic interference reduction to decrease the affection to the healthy. This paper presents a new architecture which improves the circuit spread- spectrum performance and compatible for 1.5-Gbit/s SATA [03], 3-Gbit/s SATA and 6-Gibt/s SATA specifications. Two of delta-sigma modulators were used to overcome the triangular nonlinearity issue and simplify the delta-sigma modulator design. The schematics have been implemented in a 0.18-um CMOS process which fabricated by TSMC. The output clock could reduce spectrum about 17db at 6-GHz. The size of the chip is 0.570.45 mm2 and operated at a power supply of 1.8-V.
Abstract (In Chinese) i
Abstract ii
Acknowledgment iii
Contents iv
List of Tables vi
List of Figures vii

Chapter 1 Introduction 1
1.1 Motivation and Related Background 1
1.2 Thesis Organization 2
Chapter 2 The Spread Spectrum Clock Generator Architecture 4
2.1 The Spread-Spectrum Clock Generator (SSCG) Introduction 4
2.2 Overview of Spread Spectrum Clock Generator Architecture 5
2.2.1 SSCG of changing the divider N1/N2 number 6
2.2.2 Output Stage directly modulated SSCG 7
2.2.3 Low-Pass Filter modulated SSCG 8
2.3 Summary 9

Chapter 3 The SSCG Architecture of 6-Gbit/s SATA 10
3.1 The Introduction of SSCG for 6-Gbit/s SATA 10
3.2 The Phase-Locked Loop of 6-Gbit/s SATA System 10
3.2.1 The Third-Order Phase-Locked Loop System 12
3.2.2 The Fourth-Order Phase-Locked Loop System 15
3.2.3 The Regulator for Fourth-Order PLL 18
3.3 The Proposed SSCG Architecture of 6-Gbit/s SATA System 23
3.3.1 The Proposed SSCG Architecture Principle of 6-Gbit/s SATA 23
3.3.2 The Traditional SSCG Architecture Principle of 6-Gbit/s SATA 25
3.3.3 The Comparison of Proposed and Traditional SSCG Architecture 27
3.4 Summary 31

Chapter 4 The Circuits Implementation and Simulated Results 32
4.1 The Introduce of Proposed Architecture Circuits 32
4.2 The Phase-Frequency Detector Circuit 32
4.2.1 The implementation of PFD 33
4.2.2 The Simulated Results of PFD 34
4.3 The Charge Pump Circuit 35
4.3.1 The Implementation of Charge Pump 36
4.3.2 The Simulated Results of Charge Pump 37
4.4 The Divider Circuit 39
4.4.1 The High Speed divided-by-2 Current-Mode Divider 39
4.4.2 The variable divided Number (14.5/15) Divider 42
4.5 The LC-VCO Circuit 45
4.5.1 The implementation of LC-VCO Circuit 45
4.5.2 The Simulated Results of LC-VCO Circuit 46
4.6 The Digital ΔΣ Modulator 50
4.6.1 The First-Stage Digital ΔΣ Modulator 50
4.6.2 The Second Stage Digital ΔΣ Modulator 51
4.7 The 6-Gbit/s SATA SSCG 52
4.7.1 The Simulation of controlled-voltage and output spectrum 52
4.7.2 The Comparison with other publications 53
4.8 Summary 54

Chapter 5 The Circuits Layout and Chip Measurement 56
5.1 The Circuits Layout and Floor Plan 56
5.2 The Chip Measurement 61
5.2.1 Testing Setup and Experimental Results 61
5.2.2 Measurement Discussion 64
5.3 Summary 64

Chapter 6 Conclusions and Future Works 65
6.1 Conclusions 65
6.2 Recommended Future Works 66

References 68
[01] K. B. Hardin, J. T. Fessler, and D. R. Bush, “Spread-spectrum clock generation for the reduction of radiated emissions,” in Proc. IEEE Int. Symp. Electromagnetic Compatibility, pp. 227-231, 1994.
[02] J. Y. Michel and C. Neron, “A frequency modulated PLL for EMI reduction in embedded application,” in Proc. IEEE Int. ASIC/SOC Conf., pp. 362-365, 1999.
[03] M. Sugawara et al., “1.5-Gb/s 5150-ppm spread-spectrum SerDes PHY with a 0.3-mW 1.5-Gb/s level detector for serial ATA,” in Symp. VLSI Circuits Dig. Tech. Papers, pp. 60-63, June 2002.
[04] H. S. Li, Y. C. Cheng, and D. Puar, “Dual-loop spread-spectrum clock generator,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 184 -185, 1999.
[05] Y. Moon, D. K. Jeong, and G. Kim, “Clock dithering for electromagnetic compliance using spread-spectrum phase modulation,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 186-187, 1999.
[06] H. Mair and L. Xiu, “An architecture of high-performance frequency and phase synthesis,” IEEE J. Solid-State Circuits, vol. 35, pp. 835-846, June 2000.
[07] H. W. Chen and J. C. Wu, “A spread-spectrum clock generator for EMI reduction,” IEICE Trans. Electron, pp. 1959-1966, Dec. 2001.
[08] H. H. Chang; I. H. Hua, and S. I. Liu, “A spread-spectrum clock generator with triangular modulation,” IEEE J. Solid-State Circuits, vol. 38, pp. 673-676, Apr. 2003.
[09] B. Razavi, RF Microellectronics, Prentice Hall, 1998.
[10] B. Razavi, Design of Analog CMOS Integrated Circuits, McGRAW-Hall, New York, 2001.

[11] Roland E. Best, “Phase-Locked Loops Design, Simulation, and Applications,” McGRAW- Hall, 2001.
[12] E. Alon, J. Kim, S. Pamarti, K. Chang, and M. Horowitz, “Replica Compensated Linear Regulator for Supply-Regulated Phase-Locked Loops,” IEEE J. Solid-State Circuits, vol. 41, pp. 413-424, Feb. 2006.
[13] T. C. Lee and B. Razavi, “A stabilization technique for phase-locked frequency synthesizers,” in IEEE Symposium on VLSI Circuit Dig. Tech. Papers, pp. 39-42, June 2001.
[14] Z. X. Zhang, H. Du, and M. S. Lee, “A 360-MHz 3V CMOS PLL with 1V Peak-to-Peak Power Supply Noise Tolerance,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 134-135, Feb. 1996.
[15] J. E. Parker and D. Ray, “A 1.6-GHz CMOS PLL with On-Chip Loop Filter,” IEEE J. Solid-State Circuits, vol. 33, pp. 337-343, Mar. 1998.
[16] J. G. Maneatis, J. Kim, I. McClatchie, J. Maxey, and M. Shankaradas, “Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL,” IEEE J. Solid-State Circuits, vol. 38, pp. 1795-1803, Nov. 2003.
[17] T. H. Lee, K. S. Donnelly, J. T. C. Ho, J. Zerbe, M. G. Johnson, and T. Ishikawa, “A 2.5V CMOS delay-locked loop for an 18Mbits, 500MB/s DRAM,” IEEE J. Solid-State Circuits, vol. 29, pp. 1491-1496, Dec. 1994.
[18] S. Kim, K. Lee, Y. Moon, D. K. Jeong, Y.Choi, and H. K. Lim, “A 960-Mb/s/pin interface for skew-tolerant bus using low-jitter PLL,” IEEE J. Solid-State Circuits, vol. 32, pp. 691-700, May 1997.
[19] J. G. Maneatis, “Low-jitter process-independence DLL and PLL based on self-biased techniques,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 130-131, Feb. 1996
[20] C. Lam and B. Razavi, “A 2.6-GHz/5.2GHz frequency synthesizer in 0.4-μm CMOS technology,” IEEE J. Solid-State Circuits, vol. 35, pp. 788-794, May 2000.
[21] T. K. K. Kan, G. C. T. Leung, and H. C. Luong, “A 2-V 1.8-GHz fully integrated CMOS dual-loop frequency synthesizer,” IEEE J. Solid-State Circuits, vol. 37, pp. 1012-1020, Aug. 2002.
[22] C. W. Lo and H. C. Luong, “A 1.5-V 900-MHz monolithic CMOS fast-switching f requency synthesizer for wireless applixations,” IEEE J. Solid-State Circuits, vol. 37, pp. 459-470, Apr. 2002.
[23] C. Lam and B. Razavi, “A 2.6GHz/5.2-GHz CMOS VCO,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 402-403, 1999.
[24] M. kurisu, G. Uemura, M. Ohuchi, C. Ogawa, H. Takemura, T. Morikawa, and T. Tashiro, “A Si Bipolar 28-GHz Dynamic Frequency Divider,” IEEE J. Solid-State Circuits, vol. 27, pp. 1799-1804, Dec.1992.
[25] A. W. Buchwald, K. W. Martin, A. K. Oki, and K. W. Kobayashi, “A 6-GHz Integrated Phase-Locked Loop Using ALGaAs/GaAs heterojunction Bipolar Transistors,” IEEE J. Solid-State Circuits, vol. 27, pp. 1752-1762, Dec. 1992.
[26] J. Craninckx and M. S. J. Steyaert, “A 1.75-GHz/3V dual-modulus divide-by-128/129 prescaler in 0.7-um CMOS,” IEEE J. Solid-State Circuits, vol. 31, pp. 890-897, July 1996.
[27] S. L. Luand M. Ercegovac, “A novel CMOS implement of double-edge- triggered flip-flops,” IEEE J. Solid-State Circuits, vol. 25, pp. 1008-1010, Aug. 1991.
[28] P. Larsson, “High-speed architecture for a programmable frequency divider and a dual-modulus prescaler,” IEEE J. Solid-State Circuits, vol. 31, no. 5, pp. 744-748, 1996.
[29] R. Hossain, L. Wrinski and A. Albicki, “Low power design using double edge triggered flip-flops,” IEEE Trans. VLSI Systems, pp. 261-265, Feb. 1994.
[30] J. Yuan and C. Svensson, “New single-clock CMOS latches and flip-flops with improved speed and power savings,” IEEE J. Solid-State Circuits, vol. 32, pp. 62-69, Oct. 1997.
[31] W. T. Chen, J. C. Hsu, H. W. Lune and C. C. Su, “A spread Spectrum Clock Generator for SATA- II,” ISCAS, pp. 2643-2646, Mar. 2005.
[32] M. Kokubo, T. Kawamoto, T. Osima, “Spread-Spectrum Clock Generator for Serial ATA using Fractional PLL Controlled by ΔΣ Modulator with Level Shifter,” IEEE Interational Solid-State Circuit Conference, pp. 160-161, Feb. 2005.
[33] H. R. Lee, O. Kim, G. Ahn, “A Low-jitter 5000ppm Spread Spectrum Clock Generator for Multi-channel SATA Transceiver in 0.18um CMOS,” IEEE Interational Solid-State Circuit Conference, pp. 162-163, Feb. 2005.
[34] J. Shin, I. Seo, J. Y. Kim, S. H. Yang, “A Low-jitter Added SSCG with Seamless Phase Selection and Fast AFC for 3rd Generation Serial-ATA,” IEEE Custom Intergrated Circuit Conference, pp. 409-412, 2006.
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