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研究生:楊鈞麟
研究生(外文):Chun-Lin Yang
論文名稱:考慮群集錯誤之嵌入式記憶體內建自我修復電路
論文名稱(外文):Efficient BISR Techniques for Embedded Memories Considering Cluster Faults
指導教授:呂學坤
指導教授(外文):Shyue-Kung Lu
學位類別:碩士
校院名稱:輔仁大學
系所名稱:電子工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:英文
論文頁數:57
中文關鍵詞:群集錯誤嵌入式記憶體內建自我修復
外文關鍵詞:cluster faultsembedded memoriesBISR
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在現今深次微米技術的時代,system-on-a-chip 的密度以及容量正在明顯的增加當中。此外,嵌入式記憶體在SOC當中經常佔有絕大部分的面積,嵌入式記憶體的良率將主宰著整個SOC的良率。基於上述理由,對於設計者以及製造者而言,改善嵌入式記憶體良率的方法變成一個最重要的議題。ㄧ個新穎的全域區塊備用資源架構的內建自我修復方法在此篇論文中被提出,備用行以及備用列被切割成行備用區塊以及列備用區塊,因此,故障記憶體細胞的修復可以在列備用區塊以及行備用區塊的層級來修復。此外,行備用區塊以及列備用區塊可用來替換記憶體陣列中位於任何一個位址上的故障記憶體細胞。這個全域的特性對於修復群集錯誤也是有幫助的,此種被提出的備用資源架構很容易整合在內嵌式記憶體中。基於此種全域的備用資源架構,一個適合於內建式實現的heuristic MESP演算法被提出。依據實驗結果,實現MESP演算法的額外硬體是幾乎可以被忽略的。由於有效率的使用備用資源,製造的良率、修復率以及可靠度可被明顯的改善。
In today’s deep sub-micron technology era, the density and capacity of the system-on-a-chip (SOC) is increasing significantly. Moreover, embedded memories usually occupy the greatest part of the SOC. The yield of the embedded memories will dominate the SOC yield. Based on these reasons, methodologies for yield improvement of embedded memory are becoming the most important issues for the designer and manufacturer. A novel Built-In Self-Repair (BISR) scheme with global-block-based redundancy architectures is proposed in this thesis. The redundant rows/columns are divided into row/column blocks. Therefore, the repair of faulty memory cells can be performed at the row/column block level. Moreover, the redundant row/column blocks can be used to replace faulty cells anywhere in the memory array. This global characteristic is helpful for repairing cluster faults. The proposed redundancy architecture can be easily integrated with the embedded memory cores. Based on the proposed global redundant architecture, a heuristic MESP (modified essential spare pivoting) algorithm suitable for built-in implementation is also proposed. According to experimental results, the hardware overhead for implementing the MESP algorithm is almost negligible. Due to the efficient usage of the redundancy, the manufacturing yield, repair rate, and reliability can all be improved significantly.
Abstract (in Chinese) ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ i
Abstract ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ ii
Acknowledgement (in Chinese) ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ iii
Contents ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ iv
List of Tables ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ vi
List of Figures ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ vii
1 Introduction ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 1
1.1 Motivation and Background ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 1
1.2 Organization ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 4
2 Review of Built-In Self-Repair Schemes for Embedded Memories ‧‧‧‧ 6
2.1 Review of Divided Word-Line and Divided Bit-Line Structures ‧‧‧ 6
2.2 Built-In Self-Test ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 8
2.3 Built-In Redundancy Analysis and Built-In Self-Repair Techniques ‧ 9
3 An Efficient Built-In Self-Repair Scheme with Global Block-Based Redundancy ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 14
3.1 Global Block-Based Redundancy Architecture ‧‧‧‧‧‧‧‧‧‧ 14
3.2 Modified Essential Spare Pivoting Algorithm ‧‧‧‧‧‧‧‧‧‧ 16
3.3 An Example ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 19
4 A Simulator for Built-In Redundancy Analysis ‧‧‧‧‧‧‧‧‧‧‧‧ 23
4.1 Simulation Flow ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 23
4.2 Defect Distribution Models and Fault Models ‧‧‧‧‧‧‧‧‧‧ 26
4.3 Evaluation of Repair Rate ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 31
4.4 Hardware Overhead ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 35
4.5 Yield Analysis ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 37
5 Physical Design ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 43
5.1 Architecture of the BISR Circuits Based on MESP Algorithm ‧‧‧‧ 43
5.2 Physical Design of the EESP Algorithm ‧‧‧‧‧‧‧‧‧‧‧ 47
6 Conclusions and Future Works ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 53
6.1 Conclusions ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 53
6.2 Future Works ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 53
References ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 54
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