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研究生:董茂揚
研究生(外文):Mao-Yang Dong
論文名稱:動量估測運算陣列之可測試性設計及容錯技術
論文名稱(外文):Design-for-Testability and Fault-Tolerant Techniques for Motion Estimation Computing Arrays
指導教授:呂學坤
指導教授(外文):Shyue-Kung Lu
學位類別:碩士
校院名稱:輔仁大學
系所名稱:電子工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:英文
論文頁數:68
中文關鍵詞:可測試性設計容錯技術動量估測
外文關鍵詞:Design-for-TestabilityFault-TolerantMotion Estimation
相關次數:
  • 被引用被引用:0
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  • 下載下載:15
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動量估測 (Motion Estimation, ME) 為影像編碼系統中主要的運算,也是運算最密集的部份。由於簡單性以及規律性,區塊匹配 (Block-matching) 演算法被廣泛的使用於計算動作向量 (Motion Vectors, MVs)。隨著 VLSI 技術的發展,動量估測運算陣列可能整合為單一晶片或單晶片系統 (System-on-chip, SOC)。然而,將大量的運算單元 (Processing Elements, PEs) 整合在單一晶片或 SOC 中會將低測試的效率。為了解決這些問題,我們在本篇論文中提出針對二維動量估測運算陣列之可測試性設計。我們以 C-Testability 條件為基礎提出二種可測試的 ME 設計於位元階層 (Type-I TMEbit and Type-II TMEbit)。我們的 C-Testability 條件針對單一細胞錯誤 (Single cell faults) 的錯誤涵蓋率 (Fault Coverage) 約可達到 100%。以 Type-I TMEbit 為基礎,我們提出在位元階層之容錯設計。另外,我們也提出在模組階層之容錯設計。為了驗證所提出的方法,我們將實現以 Type-I TMEbit 為基礎之晶片並且使用 TSMC 0.18 m 製程技術加以實現。根據實驗結果,邏輯閘 (gate count) 數目約為 159 K 且電路可以操作在 100 MHz 的頻率。而且額外的硬體成本約為 7%。
Motion estimation (ME) is the main computation used in video coding systems and it is also the most computation-intensive part. Because of the simplicity and regularity, the block-matching algorithms are widely used for the computation of motion vectors (MVs). With the advance of VLSI technology, integration of the ME computing array into a single chip or a system-on-chip (SOC) design is becoming possible. However, integrating a large number of processing elements (PEs) on a single chip or SOC results in the increase in the logic-per-pin ratio, which drastically reduces the efficiency of testing the logic on the chip. In order to deal with these problems, design-for-testability techniques for 2-D motion estimation computing arrays are proposed in this thesis. We propose two types of testable motion estimation (TME) designs at the bit level (Type-I TMEbit and Type-II TMEbit) based on the C-testability conditions. Our C-testability conditions guarantee about 100% fault coverage for single cell faults with a constant number of test patterns. Based on the Type-I TMEbit testable design, a fault-tolerant and testable design at the bit level (FTMEbit) is also proposed. We also propose a fault-tolerant approach at the AD module level (FTMEAD). In order to validate the proposed techniques, an experimental chip for Type-I TMEbit is implemented with TSMC 0.18 m technology. According to experimental results, the gate count of the design is about 159 K, and the design can operate at the frequency up to 100 MHz. The hardware overhead is about 7%.
1 Introduction ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 1
1.1 Motivation ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 1
1.2 Organization ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 7
2 Review of Motion Estimation Algorithms and Architectures ‧‧‧‧‧ 8
2.1 Block-Matching Algorithms ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 8
2.1.1 Full-Search Block-Matching Algorithm ‧‧‧‧‧‧‧‧‧ 9
2.1.2 Fast Block-Matching Algorithms ‧‧‧‧‧‧‧‧‧‧‧ 11
2.1.2.1 Three-Step Search Algorithm ‧‧‧‧‧‧‧‧‧‧ 11
2.1.2.2 The 2-D Logarithmic Search Algorithm ‧‧‧‧‧‧ 12
2.1.2.3 The Conjugate Direction Search Algorithm ‧‧‧‧ 13
2.1.2.4 The Diamond Search Algorithm ‧‧‧‧‧‧‧‧ 14
2.2 Hardware Architectures ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 16
2.2.1 1-D Array Architectures ‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 17
2.2.2 2-D Array Architectures ‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 19
3 Review of C-testability and M-testability Conditions ‧‧‧‧‧‧‧‧ 25
4 Testable Designs for Motion Estimation Computing Arrays ‧‧‧‧‧ 28
4.1 Bit-Level Testable Design ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 28
4.1.1 Type-I Testable Design for ME Computing Array ‧‧‧‧ 28
4.1.2 Type-II Testable Design for ME Computing Array ‧‧‧‧ 35
4.2 Module-Level Testable Design ‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 40
5 Fault Tolerance Techniques ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 43
5.1 Fault Tolerance Design at the Bit Level ‧‧‧‧‧‧‧‧‧‧‧ 43
5.2 Fault Tolerance Design at the Module Level ‧‧‧‧‧‧‧‧‧ 46
6 Experimental Results ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 49
6.1 Design Flow ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 50
6.2 Reliability and Hardware Overhead Analysis ‧‧‧‧‧‧‧‧‧ 54
6.3 Simulation Results ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 60
7 Conclusions and Future Works ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 63
7.1 Conclusions ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 63
7.2 Future Works ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 64
[1]ISO/IEC 11172-2, “Coding of Moving Pictures and Associated Audio for Digital Storage Media at up to About 1.5 Mbit/s: Part 2 - Video,” International Standard, August 1993.
[2]Joan L. Mitchell, William B. Pennebaker, Chad E. Fogg, and Didier J. LeGall, “MPEG Video Compression Standard,” International Thomson Publishing, 1997.
[3]ISO/IEC JTC1/SC29/WG11 Draft CD 13818-2, “General Coding of Moving Pictures and Associated Audio,” International Standard, 1994.
[4]MPEG Requirements Group, “MPEG-4 Overview Document,” Document ISO/IEC JTC1/SC29/WG11/N2725, Seoul MPEG meeting, March 1999.
[5]ITU-T Rec. H.261, “Video Codec for Audiovisual Services at p×64 kbits/s,” Mar. 1993.
[6]ITU-T Rec. H.263, “Video Coding for Low Bit Rate Communication,” January 1998.
[7]Karel Rijkse, KPN Research, “H.263: Video Coding for Low-Bit-Rate Communication,” IEEE Communication Magazine, pp. 42-45, December 1996.
[8]Thomas Wiegand, Gary J. Sullivan, Gisle Bjontegaard, and Ajay uthra,“Overview of the H.264/AVC Video Coding Standard,” IEEE Trans. Circuits and Syst. for Video Technology, July 2003.
[9]Vasudev Bhaskaran and Konstantinos Konstantinides, Image and Video Compression Standards: Algorithms and Architectures, Kluwer Academic Publishers, 1997.
[10]C. Cafforio and F. Rocca, “Methods for measuring small displacements of television images,” IEEE Trans. Inform. Theory, vol. IT-22, no. 5, pp. 573-579, Sept. 1976.
[11]H. G. Musmann, P. Pirsch, and H. J. Grallert, “Advances in picture coding,” Proc. IEEE, vol. 73, pp. 523-548, Apr. 1985.
[12]T. Koga et al., “Motion-compensated interframe coding for video conferencing,” in Proc. Nat. Telecommunications Conf., pp. G 5.3.1-G 5.3.5, Nov. - Dec. 1981.
[13]J. R. Jain and A. K. Jain, “Displacement measurement and its application in interframe image coding,” IEEE Trans. Commun., vol. COM-29, pp. 1799-1808, Dec. 1981.
[14]R. Srinivasan and K. R. Rao, “Predictive coding based on efficient motion estimation,” IEEE Trans. Commun., vol. COM-33, pp. 1011-1014, Sept. 1985.
[15]S. Zhu and K. -K. Ma, “A new diamond search algorithm for fast block matching motion estimation,” in Proc. Int. Conf. Inform., Commun., Signal Process., Singapore, pp. 292-296, Sept. 9-12, 1997.
[16]S. Zhu and K.-K. Ma, “A new diamond search algorithm for fast block-matching motion estimation,” IEEE Trans. Image Processing, vol. 9, pp. 287-290, Feb. 2000.
[17]W. P. Marnane and W. R. Moore, “Testing a motion estimator array,” in Proc. Int’l Conf. Application Specific Array Processors, pp. 734-745, 1990.
[18]Donglin Li, Mingzeng Hu and O. A. Mohamed, “Built-in self-test design of motion estimation computing array,” in Proc. 2nd Annu. IEEE Northeast Workshop on Circuit and Systems, pp. 349-352, June 2004.
[19]K. M. Yang, M. T. Sun, and L. Wu, “A family of VLSI designs for the motion compensation block-matching algorithm,” IEEE Trans. Circuits and Syst., vol. 36, no. 10, pp. 1317-1325, Oct. 1989.
[20]Seung Hyun Nam and Moon Key Lee, “Flexible VLSI architecture of motion estimator for video image application,” IEEE Trans. Circuits and Syst. II, vol. 43 no. 6, pp. 467-470, Jun. 1996.
[21]T. Komarek and P. Pirsch, “Array architectures for block matching algorithms,” IEEE Trans. Circuits and Syst., vol. 36, no. 10, pp. 1301-1308, Oct. 1989.
[22]L. De Vos and M. Stegherr, “Parameterizable VLSI architectures for the full-search block-matching algorithm,” IEEE Trans. Circuits and Syst., vol. 36, no. 10, pp. 1309-1316, Oct. 1989.
[23]C. H. Hsieh and T. P. Lin, “VLSI architecture for block-matching motion estimation algorithm,” IEEE Trans. Circuits and Syst. Video Technol., vol. 2, no. 2, pp. 169-175, June 1992.
[24]S. K. Lu, J. S. shih and S. C. Huang, “Design-for-Testability and Fault-Tolerant Techniques for FFT Processors,” IEEE Trans. VLSI Syst., vol. 13, no. 6, June 2005.
[25]S. K. Lu, C. W. Wu and S.Y. Kuo, “Enhancing testability of VLSI arrays for fast Fourier transform," IEE Proc. Part E, vol. 140, no. 3, pp. 161-166, May 1993.
[26]C. W. Wu and P. R. Cappello, “Easily testable iterative logic arrays,” IEEE Trans. Comput., vol. C-31, no. 6, pp. 640-652, May 1990.
[27]W. H. Kautz, “Testing for faults in combinational cellular logic arrays,” in Proc. 8th Annu. Symp. Switching, Automata Theory, pp. 161-174, 1967
[28]P. R. Menon and A. D. Friedman, “Fault detection in iterative arrays,” IEEE Trans. Comput., vol. C-20, pp. 524-535, May 1971.
[29] A. D. Friedman, “Easily testable iterative systems,” IEEE Trans. Comput., vol. C-22, pp. 1061-1064, Dec. 1973.
[30]S. K. Lu, J. C. Wang and C. W. Wu, “C-testable design techniques for iterative logic arrays,” IEEE Trans. VLSI Syst., vol. 3, pp. 146-152, Mar. 1995.
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