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研究生:劉為元
研究生(外文):Wei-Yang Liu
論文名稱:頻率域之波前式位移估計器的內建自我測試
論文名稱(外文):Efficient BIST Techniques for Wavefront Array Processor for Motion Estimation and Compensation in the Transform Domain
指導教授:呂 學 坤
指導教授(外文):Shyue-Kung Lu
學位類別:碩士
校院名稱:輔仁大學
系所名稱:電子工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:中文
論文頁數:73
中文關鍵詞:內建自我測試可測試性設計位移估計
外文關鍵詞:BIST (Built-In Self-Test)Design For TestabilityMotion Estimation
相關次數:
  • 被引用被引用:0
  • 點閱點閱:64
  • 評分評分:
  • 下載下載:10
  • 收藏至我的研究室書目清單書目收藏:0
我們在本篇論文針對一個新的架構-前波式位移產生器架構提出兩種測試方法,利用前波式位移產生器內部之心脈式陣列具有連續性邏輯陣列的性質, C 可測試性與 M 可測試性分別運用在模組層次與位元層次的內建自我測試;乘法單元以及運算單元為構成心脈式陣列的兩個主要元件,由於乘法單元不具有全映至 (bijective) 的性質,因此我們將它更改後,當心脈式陣列進入測試模式時,乘法單元同樣具有全映至性質,稱之修改過的運算單元 (MPE),使得測試向量的傳遞能呈現 +45 度棋盤式棋盤形鋪嵌,再經過內建自我測試技術的修改後,讓心脈式陣列內所有的運算單元與修改過的運算單元都獲得測試項量產生器所給予的完整測試向量;模組層次的內建自我測試針對兩種單元內的乘法器給予完整的測試向量 2w (w為乘法器之字元長度) 組測試向量;而位元層次的內建自我測試則是使用文獻[20]對於 Booth 乘法器的測試技術,測試向量為 28 組,除了大幅縮減測試時間外,我們還修正了文獻內的乘法器架構之錯誤,最後使得錯誤涵蓋率於模組層次與位元層次分別達到 99.34 % 與 99.02% ,可以有效的測試前波式位移產生器,而且額外增加的面積分別只有 6% 與 4%,最後我們會將模擬與晶片實現呈現在論文當中。
Testable design techniques for a systolic motion estimator based on C-testability and M-testablility conditions are proposed in this paper. The systolic array in motion estimator can be viewed as a two-dimensional iterative logic array (ILA) which is composed of processing elements (PE) and multiplication element (MUL). The function of each multiplication element is modified to be bijective to meet the C-testable and M-testable conditions. The number of test patterns in module level is 2w, where w denotes the wordlength of a multiplier. In order to reduce testing time, the DFT technique which is proposed in [20] is used in bit level. The faults in Booth Multiplier [20] are not only detected but also corrected in this paper. The test patterns are transmitted as a 45° tessellation. The BIST in module level and bit level can achieve 99% fault coverage. In our design, faults are not only detected but also located. The total area overheads are acceptable-about 6% and 4%, respectively. To verify our approaches, an experimental chip is implemented.
中文摘要 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ i
英文摘要‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ ii
誌謝 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ iii
目錄 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ iv
表目錄 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ vii
圖目錄 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ viii
1 緒論 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 1
1.1 研究動機與背景 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 1
1.2 本文內容 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 2
2 心脈式位移估計器的回顧 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 3
2.1 頻率域之位移估計 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 3
2.2 心脈式位移估計器的硬體架構 ‧‧‧‧‧‧‧‧‧‧‧‧‧ 8
3 心脈式位移估計器之可測試性設計 (DFT) ‧‧‧‧‧‧‧‧‧‧‧ 19
3.1 在模組層次的DFT 技術 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 19
3.2 在位元層次的DFT技術 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 22
3.2.1 修正過的串列式Booth 陣列乘法器 ‧‧‧‧‧‧‧ 23
3.2.2 Booth 陣列乘法器的DFT 技術 ‧‧‧‧‧‧‧‧‧ 33
3.2.3 針對心脈式位移估計器的應用 ‧‧‧‧‧‧‧‧‧ 39
4 心脈式位移估計器之內建自我測試 (Built-In Self-Test) ‧‧‧ 41
4.1 模組層次的BIST技術 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 41
4.2 位元層次的BIST技術 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 44
4.3 錯誤定位技術 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 57
5 實驗結果 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 59
5.1 模擬結果 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 59
5.2 錯誤涵蓋率與額外的面積 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 68
5.3 晶片實現與特性 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 69
6 總結與未來工作 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 71
6.1 總結 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 71
6.2 未來工作 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 71
參考文獻 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 72
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