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研究生:劉嘉修
研究生(外文):Chia-Hsiu Liu
論文名稱:嵌入式記憶體低功率內建自我測試技術之研究
論文名稱(外文):Low-Power Built-in Self-Test Techniques for Embedded SRAMs
指導教授:呂學坤
指導教授(外文):Shyue-Kung Lu
學位類別:碩士
校院名稱:輔仁大學
系所名稱:電子工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:英文
論文頁數:70
中文關鍵詞:內建自我測試記憶體低功率
外文關鍵詞:Built-in Self-TestSRAMsLow-Power
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  • 被引用被引用:0
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  • 下載下載:25
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隨著越多的內嵌式記憶體同時自我測試,所造成的功率消耗將明顯上升。為了解決這個問題,我們提出了重新排序位址技術和列區塊預充電技術來降低記憶體在測試時的功率消耗。在測試模式時,重新排序位址技術,並使用單一位元改變 (single-bit-change) 之計數器來取代二進制計數器。此技術將有效降低位址線上的平均功率與最大功率。除此之外,我們也提出一個列區塊預充電技術,此技術是建構在分割字位元線 (divided world line) 技術架構下。在低功率測試模式下,我們只預充正在存取的列區塊,來取代原本預充整個記憶體陣列。這將造成預充電路上的功率消耗明顯下降。我們使用TSMC 0.18 μm製程去實現了一個2K位元的記憶體晶片,此晶片整合了階層式位元線與局部感測放大器技術和列區塊預充電技術。根據實驗結果指出,對於一個256 × 256位元導向的記憶體,列區塊預充電技術將可降低48.9% 的功率消耗。此外,當列區塊的數量增加時,功率節省程度也將增加。
The severity of power consumption during parallel BIST of embedded memory cores is growing significantly. In order to alleviate this problem, an address sequence reordering technique and a row bank-based pre-charge technique are proposed for low-power testing of embedded SRAMs. Address sequence reordering technique uses the single-bit-change (SBC) counter to replace the binary counter during the test mode. It will effectively decrease the average and peak power of the address lines. Besides, a row bank-based pre-charge technique based on the DWL (divided world line) architecture is proposed. In low-power test mode, instead of pre-charging the entire memory array, only the current accessed row bank is pre-charged. This will result in significant power saving for the pre-charge circuitry. An SRAM chip with 2 Kbits is implemented with TSMC 0.18 μm process. It integrates the hierarchical bit line with local sense amplifier technique and row bank-based pre-charge technique. According to experimental results, 48.9% power reduction can be achieved for a 256 × 256 bit-oriented SRAM. Moreover, if the number of row banks increases, the power saving will also increase.
Contents

Page
Abstract (in Chinese) ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ i
Abstract ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ ii
Acknowledgement ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ iii
Contents ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ iv
List of Tables ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ v
List of Figures ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ vi
1 Introduction ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 1
1.1 Motivation and Background ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 1
1.2 Organization ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 4
2 Address Sequence Reordering ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 5
2.1 Power Consumption Mechanisms ‧‧‧‧‧‧‧‧‧‧‧‧‧ 6
2.2 Modified BIST Circuit ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 8
2.3 Fault Coverage of Test Algorithms ‧‧‧‧‧‧‧‧‧‧‧ 19
3 Row Bank-Based Pre-charge Techniques ‧‧‧‧‧‧‧‧‧‧‧ 29
3.1 Review of DWL Architecture ‧‧‧‧‧‧‧‧‧‧‧‧‧ 29
3.2 Reducing Pre-charge Activity Based on DWL Architecture ‧‧‧ 32
3.3 Design of the Control Circuitry ‧‧‧‧‧‧‧‧‧‧‧‧‧ 34
3.4 Hardware Overhead Analysis ‧‧‧‧‧‧‧‧‧‧‧‧‧ 37
4 Integration of Low-Power Techniques ‧‧‧‧‧‧‧‧‧‧‧‧‧ 40
4.1 Review of Hierarchical Bit-Line Techniques and Local Sense ‧
Amplifiers ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 40
4.2 Integrated Architecture ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 47
5 Experimental Results ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 52
5.1 Architecture Implementation ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 52
5.2 Hardware Overhead Analysis ‧‧‧‧‧‧‧‧‧‧‧‧‧ 59
5.3 Comparisons ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 64
6 Conclusions ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 67
6.1 Conclusions ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 67
References ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 68
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