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研究生:蔡宜叡
研究生(外文):Jui-Yi Tsai
論文名稱:全數位式時間數位轉換器
論文名稱(外文):All Digigtal Time-To-Digital Converter
指導教授:呂學坤黃弘一
指導教授(外文):Shyue-Kung LuHong-Yi Huang
學位類別:碩士
校院名稱:輔仁大學
系所名稱:電子工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:中文
論文頁數:96
中文關鍵詞:全數位時間數位轉換器
外文關鍵詞:all digitaltime-to-digital converter
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所提出的高解析度時間數位轉換器的架構得到解析度範圍為1.6ps~16ps且整體電路的可輸入的量測範圍為0.4ns ~ 2.01ns,即可測試訊號頻寬為500MHz~2.5GHz,電路採用TSMC 0.18um 1P6M CMOS製程,利用兩級電路的方式提高轉換率為約5ns,參考頻率的操作範圍為255MHz~290MHz。此架構使用全數位的方式即可使其只需要用到一組DLL,不僅有傳統架構的所有優點之外,並可改變電路的解析度大小,且在相同製程下得到較小的面積,較低的功率消耗,並且DLL鎖定的狀態時,輸出訊號可以跟隨不同脈波寬度之輸入訊號改變,可以馬上轉換出所對應到的9bits輸出數位碼,即為即時(Real time) 轉換輸出訊號之特色。當本設計應用於Frequency to Digital Converter(FDC)的應用時,可使週期性訊號中的Jitter對電路的影響根據DLL的級數增加而減低,提升FDC的解析度。
在電路設計與佈局採用TSMC 0.18um 1P6M CMOS製程,全數位式時間數位轉換器的晶片佈局核心面積為0.547×0.271mm2,功率消耗為6.84mW。
The proposed high resolution Time to Digital Converter (TDC) has a resolution between 1.6ps~16ps, and has an input range between 0.4ns ~ 2.01ns which is equivalent to a frequency of 2.5GHz and 500MHz respectively. The architecture can operate with a frequency 500MHz~2.5GHz. The circuit is implemented using TSMC 0.18um 1P6M CMOS process. The architecture adopts two stages to increase the conversion rate about 5ns with a reference frequency of 255MHz~290MHz. The architecture is based on all digital using a DLL which has the advantage of conventional designs and also an adjustable resolution, obtaining low area overhead and low power dissipation. As the DLL is locked, the output signal changes according to different input pulse width, and obtaining 9 bits output code instantly which is real time. The proposed architecture can be used as Frequency to Digital Converter (FDC), the effect of the jitter of a periodic signal is reduced as increasing the stages of the DLL achieving the resolution of the FDC.
The proposed architecture is implemented using TSMC 0.18um 1P6M CMOS process. The core area is 0.547×0.271mm2 and the total power dissipation is 6.84mW.
目錄

中文摘要…………………………………………………………………….…………..i
英文摘要……………………………………………………………….…………….....ii
誌謝…………………………………………………………..……………………..….iii
目錄……………………………………………………………….………………..…..iv
表目錄………………………………………………………………………………….vi
圖目錄…………………………………………………………………………………vii

第一章 導論
1.1 研究動機與目的…………………………………………………..1
1.2 設計考量…………………………………………………………..3
1.3 論文組織…………………………………………………………..3
第二章 時間數位轉換器先前技術探討
2.1 簡介……………………………………………………………….5
2.2 時間轉換電壓之時間數位轉換器………………………………..5
2.3 雙斜率之時間數位轉換器………………………………………..4
2.4 延遲線為基礎之時間數位轉換電路………………………………7
2.5 脈衝縮減延遲元件之時間數位轉換器……………………………9
2.6 游標尺延遲線之時間數位轉換器………………………………...10
2.7 單級游標尺元件之時間數位轉換器…………………………….12
2.8 兩級游標尺延遲線之時間數位轉換器………………………….14
2.9 結論與結果比較………………………………………………….19
2.10 TDC相關技術之應用…………………………………………...20
第三章 全數位式時間數位轉換器
3.1 全數位式時間數位轉換器架構分析…………………………….22
3.2 數位控制延遲鏈…………………………………………………...25
3.3 多相位偵測器……………………………………………………...27
3.4 游標尺偵測器………………………………………………………31
3.5 延遲鎖相迴路………………………………………………………32
3.6 全數位式時間數位轉換器理論分析………………………………35
第四章 晶片佈局與佈局後模擬
4.1 全數位式時間數位轉換器電路佈局…………………………….42
4.2 延遲鎖相迴路電路佈局…….……………………………………43
4.3 輸入級電路………………………………………………………..45
4.4 第一級電路…………………………………………………………46
4.5 第二級電路…………………………………………………………48
4.6 晶片佈局後模擬…………………………………………………...51
4.6.1 角落驗證……………………………………………………..51
4.6.2 規格表……………………………………………………….51
4.6.3 測試考量…………………………………………………….53
4.7 測量結果…………………………………………………………..56
第五章 總結與未來研究方向
5.1 總結………………………………………………………………..58
5.2 未來研究方向……………………………………………………..59
參考文獻………………………………………….……………………………………60

附件
投稿論文…………………………………………………………………………62
簡歷………………………………………………………………………………96
參考文獻
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[2] K. Park and J. Park, “20 ps resolution time-to-digital converter for digital storage oscilloscopes,” in Proc. IEEE Nuclear Science Symp., pp. 876-881, 1998.

[3] T. Xia, H. Zheng, J. Li and G. A, ”Self-Refereed On-Chip Jitter Measurement Circuit Using Vernier Oscillators,” in Proc. IEEE Computer Society Annual Symp., pp. 218-223, 2005.

[4] E. R. Ruotsalainen, T. Rahkonen and J. Kostamovaara “A Time Digitizer with Interpolation Based on Time-to-Voltage Conversion,” In Proc. 40th Midwest Symposium on Circuits and Systems, pp. 197-200, 1997.

[5] R. B. Staszewski, D. Leipold, C.-M. Hung, and P. T. Balsara, “TDC-based frequency synthesizer for wireless applications,” in Proc. IEEE Radio Frequency Integrated Circuits Symp., pp. 215-218, 2004.

[6] R. B. Staszewski and S. Vemulapalli, “1.3 V 20 ps Time-to-Digital Converter for Frequency Synthesis in 90-nm CMOS,” IEEE Trans. on Circuits and Systems—II, vol. 53, No. 3, Mar. 2006.

[7] E. R. Ruotsalainen, T. Rahkonen, and J. Kostamovaara, “An Integrated Time-to-Digital Converter with 30-ps Single-Shot Precision,” IEEE J. Solid-State Circuits, vol. 35, No. 10, Oct. 2000.

[8] P. Dudek, “A High-Resolution CMOS Time-to-Digital Converter Utilizing a
Vernier Delay Line,” IEEE Trans. on Solid-State Circuits, vol. 35, No. 2, Feb. 2000.

[9] A. H. Chan, “A Jitter Characterization System Using a Component-Invariant
Vernier Delay Line,” IEEE Trans. on VLSI Systems, vol. 12, No. 1, Jan. 2004.

[10] C. S. Hwang and Student Member, “A High-Precision Time-to-Digital Converter Using a Two-Level Conversion Scheme,” IEEE Trans. on Nuclear Science, vol. 51, No. 4, Aug. 2004.

[11] K. Karadamoglou and N. P. Paschalidis, “An 11-bit High-Resolution and Adjustable-Range CMOS Time-to-Digital Converter for Space Science Instruments,” IEEE J. Solid-State Circuits, vol. 39, No. 1, Jan. 2004.

[12]李谷桓,「兩級式游標尺延遲線時間數位轉換器」,碩士論文,國立清華大學,新竹,2003。

[13] H. Y. Huang, S. D. Wu and Y. J. Tsai, “A New Cycle-Time-to-Digital Converter with Two Level Conversion Scheme,” in Proc. IEEE International Symposium Circuits and Systems, 2007.

[14] C. C. Tsai and C. L. Lee, “An on-chip jitter measurement circuit for the PLL,” Test Symposium, pp. 332-335, Nov. 2003.

[15] B. Nelson and M. Soma, “On-chip calibration technique for delay line based BIST jitter measurement,” in Proc. IEEE International Symposium on Circuits and Systems, pp.1944-1947, 2004.

[16] P. Chen, S. I. Liu and J. Wu, “A Low Power High Accuracy CMOS Time-to-Digital Converter,” in Proc. IEEE International Symp., pp. 9-12, 1997.

[17] P. Chen, S. I. Liu, “A cyclic CMOS time-to-digital converter with deep sub-nanosecond resolution,” in Proc. IEEE Custom integrated Circuits Conf., pp. 605-608, 1999.

[18] F. Bigongiari and R. Roncella, “A 250-ps Time–Resolution CMOS Multihit Time-to-Digital Converter for Nuclear Physics Experiments,” IEEE Trans. on Nuclear Science, vol. 46, No. 2, Apr. 1999.
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