臺灣博碩士論文加值系統

低雜訊放大器(Low Noise Amplifier，LNA)在通訊系統中扮演了相當重要的角色，它除了提供給後級足夠大的增益外還要儘可能的抑制雜訊，進而決定了整體接收機的雜訊指數和靈敏度。本論文是以TSMC 0.18μm 1P6M CMOS製程的RF model來研製應用於IEEE 802.11a/b/g的無線區域網路上之低雜訊放大器。電路設計上採用疊接架構，此架構的優點是具有較低的功率損耗、較高的線性度以及較好的隔離度。
本論文分為兩部分來製作LNA。第一部份為5.25GHz Single-End CMOS LNA，採用源級衰落與cascode架構所組成的電路;第二部份為2.45GHz & 5.25GHz 雙頻帶低雜訊放大器，利用單一電路實現兩個頻段，跟以往的雙頻帶低雜訊放大器最大的差異是，本論文採用切換式電路來達到雙頻帶架構，可以讓使用者自行選擇最合適的電路方式，配合外部電路的需求，進而達到低耗能以及較低的雜訊指數。其中第二部份已交由CIC下線製作完成。

Low nosie amplifier, LNA, plays a key role in communication systems. It provide both sufficient gain and low noise in the front end circuits such that the final noise figure and sensitivity of the receiver are reduced. The thesis is aimed at the design of LNA used in IEEE802.11a/b/g with TSMC 0.18 m 1P6M CMOS technology. The cascade architecture is used so that lower power comsumption, higher linearity and better isolation can be achieved.
There are two design of LNA in the thesis. The first one is 5.25GHz single-end CMOS LNA with the source degeneration and cascade architecture. The second one is dual band LNA with frequencies 2.45GHz & 5.25GHz with the same architecture. The band are selected with a PMOS switch. The dual band circuiut is taped out by CIC.

摘要 i
Abstract ii
誌謝 iii
目錄 iv
表目錄 viii
圖目錄 ix
第一章 序論 1
1.1研究動機及目的 1
1.2 IEEE 802.11規範 2
1.3論文架構 3
第二章 接收機系統架構與規格訂定 4
2.1概述 4
2.2接收機架構方式 6
2.2.1超外差式接收機 6
2.2.1.1基本架構 6
2.2.1.2鏡像干擾(Image interferer) 8
2.2.1.3半中頻問題 9
2.2.1.4中頻選擇 10
2.2.1.5二次降頻方式 11
2.2.2直接降頻接收機 12
2.2.2.1通道選擇 14
2.2.2.2本振洩漏(LO leakge) 14
2.2.2.3 LNA偶次諧波失真干擾 15
2.2.2.4直流偏差(DC offset) 15
2.2.2.5雜訊 16
2.2.2.6 IQ不匹配 17
2.2.3鏡頻抑制接收機 18
2.2.3.1 Hartley架構 19
2.2.3.2 Weaver架構 21
2.3接收機的性能指標 22
2.3.1系統性能指標分配 23
2.4系統規格制定 24
2.4.1散射參數 24
2.4.2穩定度 25
2.4.3增益 28
2.4.4非線性效應 29
2.4.4.1諧波失真 30
2.4.4.2 1dB增益壓縮點 30
2.4.4.3交互調變 32
第三章 設計高頻電路之考量 34
3.1設計流程 34
3.2雜訊考量 35
3.2.1電阻內所產生雜訊 35
3.2.2電晶體內所產生雜訊 36
3.2.2.1熱雜訊(Thermal Noise) 37
3.2.2.2閃爍雜訊(Flicker Noise) 38
3.2.3雜訊指數 39
3.3佈局考量 41
3.3.1被動與主動元件 41
3.3.1.1電阻模型(Resistor Model) 41
3.3.1.2電容模型(MIM Capacitor Model) 43
3.3.1.3電感模型(Spiral Inductor Model) 44
3.3.1.4電晶體模型(RF-MOS Model) 46
3.3.1.5銲墊模型(Bonding PADs Model) 48
3.3.2電路佈局需注意事項 51
3.3.2.1元件的擺放與走線(Placement and Routing) 51
3.3.2.2元件的仿製物與保護環(Dummy and Guard-Ring) 55
3.3.2.3是否在晶片裡加入旁路(Bypass)電容 57
3.3.2.5電源與接地端點的問題 58
3.4佈局驗證 58
3.4.1佈局驗證補充 59
第四章 切換式雙頻帶CMOS低雜訊放大器設計與實現 60
4.1前言 60
4.2架構簡介 60
4.2.1輸入匹配方式 61
4.3設計流程 63
4.3.1低雜訊放大器設計方式 63
4.3.1.1設計步驟 64
4.3.1.2模擬結果 68
4.3.2切換式雙頻帶CMOS低雜訊放大器設計 70
4.3.2.1架構簡介 70
4.3.2.2切換式雙頻帶CMOS低雜訊放大器設計流程 70
4.3.2.3切換式雙頻帶CMOS低雜訊放大器模擬結果 74
附錄A 83
第五章 實際量測 87
5.1實際量測模擬考量 87
5.1.1製程偏移考量 87
5.1.2溫度偏移考量 88
5.2測試環境簡介 93
5.3實際佈局 94
5.4實際量測結果 95
第六章 結論 96
參考文獻 97

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