臺灣博碩士論文加值系統

本論文提出使用精確增益為2開關電容式積分器的二階積分三角調變器，它能使積分三角調變器不易受到電容不匹配、熱雜訊和通道長度不匹配等因素所影響。此二階積分三角調變器使用台積電0.35μm 2P4M CMOS 製程技術實現。模擬結果在訊號為25kHz且超取樣率為64的情況下，最大信號對雜訊失真比為62dB，動態範圍為73dB，在正常操作情況下功率消耗為16.692mW。

In this thesis, a lower mismatch sigma-delta modulator using integrators with an accurate gain of 2 is presented. This sigma-delta modulator is less subjected to capacitance mismatch, thermal noise and channel length mismatch. The second order sigma-delta modulator was designed and fabricated with TSMC 0.35μm 2P4M CMOS process. The simulation results can be achieved a peak signal to noise plus distortion ratio of 62dB and a dynamic range of 73dB with a signal frequency of 25kHz and a over-sampling ratio of 64. The power consumption is about 16.692mW under normal operation.

中文摘要 i
英文摘要 ii
誌謝 iii
目錄 iv
表目錄 vi
圖目錄 vii
第一章 緒論 1
1.1 研究動機與目的 1
1.2 論文架構 2
第二章 積分三角調變器之原理 3
2.1 量化雜訊 3
2.2 超取樣技巧 4
2.3 雜訊移頻積分三角調變器 6
2.3.1 一階積分三角調變器 9
2.3.2 二階積分三角調變器 10
2.3.3 高階積分三角調變器 12
2.3.4 Interpolative積分三角調變器 13
2.3.5 MASH積分三角調變器 14
2.3.6 多位元量化積分三角調變器 16
第三章 積分三角調變器之設計 17
3.1放大器 17
3.1.1寬擺幅偏壓電路 22
3.2 開關 26
3.3 比較器 28
3.4 時脈產生器 30
3.5 精確增益為2開關電容積分器 31
3.6 二階積分三角調變器整體電路 38
第四章 二階積分三角調變器的效能與不匹配 39
4.1 模擬結果 39
4.2 電容值不匹配 42
4.3 熱雜訊 51
4.4 通道長度不匹配 58
第五章 結論與未來工作 61
5.1 結論 61
5.2 未來發展方向 61
參考文獻 62
附錄A 64

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