臺灣博碩士論文加值系統

當金氧半場效電晶體(Metal-Oxide-Semiconductor Field Effect Transistor)的尺寸進入奈米等級時，嚴重的短通道效應(Short Channel Effect, SCE)及閘極漏電流將使得業界難以再藉由縮減通道長度及閘極氧化層厚度來提昇元件的效能。因此本論文一開始將先針對環型佈植結構尋求最佳的熱退火條件以更有效的抑制短通道效應，接著再進一步的結合應力技術及不同閘極結構的應用以更增進元件的效能。
現今在抑制短通道效應方面，大多是以環型佈植結構(Halo 或稱為口袋佈植pocket implantation)為主。在元件尚未微縮至深次微米等級前，nMOSFET的Halo是以硼(Boron)為主，但當元件進入深次微米之後，硼因質量較小，在後續熱製程時易造成擴散使得局部佈植的濃度降低且佈植的profile也較差，使得抑制熱載子效應的能力降低。因此當元件進入深次微米時，nMOSFET的Halo佈植將以質量較大的銦(Indium)取代硼。但因為In的質量較大，在Halo佈植的過程容易對元件造成更多缺陷，因此為除去In-Halo佈植所造成缺陷，後續的熱退火製程是不可貨缺的。為了找出最佳的熱退火條件，本論文中針對In-Halo元件進行不同條件的熱退火製程，在一連串基本的特性量測及熱載子可靠度的實驗後，我們發現經過900℃長時間熱退火(90秒)的In-Halo元件在各項特性上皆具有顯著的提升，其在短通道效應的抑制上，成效較硼更為顯著。
由於深次微米元件所面臨的問題除了短通道效應外，因縮減閘極氧化層所造成的嚴重閘極漏電流以及通道的高濃度臨界電壓摻雜所造成的通道載子移動下降亦十分的嚴重。因此我們除了利用In-Halo結構來抑制短通道效應之外，更需利用其它的方法來提昇元件的效能。 因現今高介電系數(high K)閘極材料的技術尚不具備高可行性，因此本論文中，我們利用了閘極上方的接觸蝕刻停止層(Contact Etch Stop Layer, CESL)來對通道產生應力，藉以提昇載子的移動率。此項技術與傳統的金氧半電晶體製程相容且不需要用到矽鍺技術，因此具有更高的可行性。在實驗中，我們針對不同厚度的CESL，探討CESL厚度對元件特性及熱載子可靠度的影響，發現當CESL厚度在700 Å時，元件具有較好的特性，過厚的CESL將反而導致元件特性的退化。此外我們亦分別製作了結合CESL應變技術與凹陷式閘極(Notch Gate)、完全金屬矽化物閘極(Fully Silicide Gate, FUSI Gate)技術的元件，個別探討不同閘極結構對於元件特性的影響。經由實驗數據証實，應用了FUSI Gate及Notch Gate結構的元件其特性皆優於傳統閘極元件。

In this dissertation, first we investigated that how to efficiently suppress the short channel effects (SCE) and hot-carrier induced degradations on nano scale complementary metal-oxide-semiconductor field effect transistor (CMOSFET) by optimizing the thermal annealing process. Then, used the stressed contact etch stop layer (CESL) strain engineering to enhance the carrier mobility on 90 nm CMOSFET with different gate structures.
First, in order to further improve the suppression of SCE, we made devices with Indium (In) -Halo implantation not the conventional Boron (B) -Halo one for the heavy mass of In; which avoided the Halo-implantation diffusion caused by post thermal processes. Besides, in order to remove the damages caused by In-Halo implantation, we had made In-halo devices with three different post annealing (PA) conditions ( 900 oC-90sec、1000 oC-10sec、and 1050 oC-spiking) to find the optimum one. After various measurements, we found that the control of annealing time is more efficient than that of annealing temperature with respect to improving hot-carrier-induced device’s degradation. For In-halo nMOSFETs as well as As-halo pMOSFETs, device characteristics and hot-carrier-induced device degradation can be improved by PA particularly at medium temperatures with long time annealing (900 oC-90sec) without degrading the device performance.
Next, we applied the CESL strain engineering on devices with different gate structures; which are conventional gate, notched-gate, and Nickel (Ni) fully silicide (FUSI) gate.
For devices with conventional gate structure, we made devices with different CESL thicknesses (700 Å, 1100 Å), gate widths(0.18-10μm), and length of diffusion (LOD) to find the interactive effects and the optimum process parameters for devices performance. We found that devices with appropriate CESL thickness (700 Å), narrow gate width, and large LOD will possess the higher driving capability.
For notch-gate devices, we found that applied the CESL technique in notch gate devices will not only suppress the SCE, reduce the capacitances of overlap region and junction, but also improve the driving capability apparently in nMOSFET without increasing the device leakages seriously. For pMOSFETs, due to the inappropriate CESL induced-stress, the improvement of driving capability was less than nMOSFETs.
Finally, for devices with Ni-FUSI gate, we have made devices with/without the second CESL. After various measurements, we found that the 2nd CESL will further improve the nMOSFETs performances and no apparent degradations were occurred. But for pMOSFETs, the 2nd CESL induced tensile stress will cause apparent degradations in devices’ driving capability, leakages, and low frequency (LF) noise.

Abstract (Chinese) (1)
Abstract (English) (3)
各章中文提要 (6)
誌謝 (19)
Contents (I)
Table Captions (IV)
Figure Captions (V)

Chapter 1
Introduction
1-1 Background and Motivation 1
1-1-1 Halo Structure for Short Channel Effects Suppression 2
1-1-2 New Techniques to Enhance Device Performances 3
1-2 Preface of This Dissertation 5

Chapter 2
Efficiently Improve the Short Channel Effects and Hot Carrier Reliability in 0.1μm CMOSFETs by Indium-Halo Implanted and Post Annealing
2-1 Introduction 10
2-2 Device Fabrication and Experiment Setup 12
2-3 Results and Discussions 13
2-3-1 Non-PA Indium-Halo versus Boron-Halo for nMOSFETs 13
2-3-2 Impacts of Post Annealing Treatments and Hot-Carrier Effects for nMOSFETs 15
2-3-3 Optimum As-Halo Structure for pMOSFETs 18
2-4 Conclusions 19
Chapter 3
The Geometry Effects on Device Performances and Reliability for 90 nm SOI nMOSFETs with Tensile-Stressed Contact Etch Stop Layer
3-1 Introduction 43
3-2 Device Fabrication and Experiment Setup 45
3-3 Results and Discussions 45
3-3-1 The Thickness Effect of HS CESL film on 90 nm SOI nMOSFETs 46
3-3-2 The Geometry Effects on 90 nm CESL-strained SOI nMOSFETs 49
3-4 Conclusions 52

Chapter 4
The Impacts of High Tensile-Stressed Contact Etch Stop Layer on 90 nm CMOSFETs with Notch-Gate Structure
4-1 Introduction 75
4-2 Device Fabrication and Experiment Setup 76
4-3 Results and Discussions 77
4-3-1 Impacts of the Notch-Gate Structure for HS CESL-Induced Stress in nMOSFETs 77
4-3-2 Impacts of the Notch-Gate for The Integrity of Gate Oxide and Si/SiO2 Interface in HS CESL nMOSFETs 79
4-3-3 The Overlap Region Capacitances in HS CESL nMOSFETs with Notch-Gate Structure 80
4-3-4 Impacts of The Notch-Gate Structure for HS CESL-Induced Stress in pMOSFETs 81
4-3-5 Impacts of The Notch-Gate for The Integrity of Gate Oxide and Si/SiO2 Interface in HS CESL pMOSFETs 82
4-3-6 The Overlap Region Capacitances in HS CESL pMOSFETs with Notch-Gate Structure 83
4-4 Conclusions 83
Chapter 5
The Impacts of High Tensile-Stressed Contact Etch Stop Layer on 65 nm CMOSFETs with Nickel-Fully-Silicide Gate Electrode
5-1 Introduction 109
5-2 Device Fabrication and Experiment Setup 111
5-3 Results and Discussions 112
5-3-1 Impacts of The 2nd HS CESL on Ni-FUSI nMOSFETs 112
5-3-2 The Low Frequency Noise for Ni-FUSI nMOSFETs with/without The 2nd HS CESL 115
5-3-3 The Gate Oxide Capacitance for Ni-FUSI nMOSFETs with/without The 2nd HS CESL 116
5-3-4 Impacts of The 2nd HS CESL on Ni-FUSI pMOSFETs 116
5-3-5 The Low Frequency Noise for Ni-FUSI pMOSFETs with/without The 2nd HS CESL 119
5-3-6 The Gate Oxide Capacitance for Ni-FUSI pMOSFETs with/without The 2nd HS CESL 119
5-4 Conclusions 120

Chapter 6
Conclusions and Prospects
6-1 Conclusions 140
6-2 Prospects 142
6-2-1 High-k Gate Dielectric and Metal Gate Electrode 142
6-2-2 FinFET Structure 143

Reference 145
Appendix A Author’s Resume i
Appendix B Author’s Related Publications ii

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