臺灣博碩士論文加值系統

本論文主要利用 SimpleScalar/ARM 模擬器來研究及分析 H.264/MPEG-4 AVC 視訊編碼標準中解碼器的除區塊濾波器 (Deblocking Filter), 根據模擬結果顯示, 記憶體存取, 高度執行圖像內容的邊界分析, 以及高度適應性之濾波運算, 佔大部份除區塊濾波的運算時間及消耗功率。 為了有效提升記憶體存取效能及除區塊濾波之執行速度, 進而提升整體系統效能並減少消耗功率, 我們研究並提出一個可擴充、可重配置視窗記憶體且包含一個可同時處理垂直邊之水平濾波及水平邊之垂直濾波、及可合成並以視窗處理架構為運作基礎之超大型積體電路架構。 我們所提出之可重配置視窗處理架構有四個主要的觀念： 第一觀念是使用超大型積體電路的方式將圖像內容的邊界分析、 Alpha、 Beta、 Index表格存取電路及高度適應性之濾波電路等整合入客製化之超大型積體電路 (Table-Free Edge Filtering Engine), 第二觀念是以新奇的處理順序配合可同時處理垂直邊之水平濾波和水平邊之垂直濾波的SPA (Simultaneous processing Architecture) 硬體架構, 第三觀念是以視窗為基礎之可重配置基礎區塊記憶體(基礎區塊記憶體即4x4 basic block) 架構來減少記憶體存取次數及減少硬體成本, 最後的觀念是, 擴充水平及垂直濾波器為平行處理單元以提升整體系統效能(可提升4倍)。 研究結果顯示, 本論文所提出的以視窗為基礎之可重配置基礎4x4區塊記憶體架構之除區塊濾波器可在60Hz的工作頻率下及時處理高畫質電視(High-definition television, HDTV, 1920x1080 pixels/frame, 60 frames/sec video signals)之除區塊濾波。根據系統及記憶體存取效能比較結果顯示, 本論文所提出的平行處理視窗架構之處理速度比先前研究所提出的除區塊濾波器快7 到20 倍，且記憶體存取效能比標準軟體架構提升4倍。

In this work, we study and analyze the computational complexity of the deblocking filter in H.264/AVC decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference, content activity check operations, and filter operations are known to be very time and power consuming in the decoder of this new video coding standard. In order to improve memory performance and speed up the deblocking filter for overall system performance and power consumption, we propose a configurable, extensible, and synthesizable window-based architecture with simultaneously processing of the horizontal filtering of vertical edge and vertical filtering of horizontal edge. The proposed architecture has four major ideas. The first idea is to reduce the number of condition branch operations by implementing content activity check operations, the table-derived operations, and edge filtering operations into the Table-Free Edge Filtering Engine. The second idea is the Simultaneous Processing Architecture (SPA) with a new processing order to simultaneously process the horizontal filtering of vertical edge and vertical filtering of horizontal edge. The third idea is to reduce the number of memory references using a configurable window-based architecture with a novel processing order to simultaneously process the horizontal filtering of vertical edge and vertical filtering of horizontal edge. The last idea is to parallelize the Table-Free Edge Filtering Engine to speed up the system performance. As a result, the processing capability of the configurable window-based architecture is very appropriate for real-time deblocking of high-definition television (High-definition television, HDTV, 1920x1080 pixels/frame, 60 frames/sec video signals) video operation at 60MHz. Moreover, the system performance of our window-based architecture significantly outperforms the previous designs from 7 times to 20 times. The memory performance of the proposed architecture is improved by four times when compared to the software implementation.

摘要 IV
ABSTRACT V
ACKNOWLEDGMENTS VI
CONTENTS VII
LIST OF TABLES IX
LIST OF FIGURES X
CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 2
1.2 CONTRIBUTIONS 4
1.3 ORGANIZATION OF THIS DISSERTATION 5
CHAPTER 2 BACKGROUND AND ALGORITHM OF DEBLOCKING FILTER 6
2.1 PROCESSING ORDER 6
2.2 SAMPLE PROCESSING LEVEL 14
CHAPTER 3 COMPUTATIONAL COMPLEXITY 17
3.1 COMPUTATIONAL COMPLEXITY OF ENCODER 19
3.2 COMPUTATIONAL COMPLEXITY OF DECODER 21
CHAPTER 4 PROPOSED ARCHITECTURES 22
4.1 ARCHITECTURE 1: TABLE-FREE EDGE FILTERING UNIT 22
4.1.1 Computation of Boundary Strength 23
4.1.2 Filtering Operation 25
4.1.3 Clipping Operation 27
4.1.4 Content Activity Check Operation 28
4.1.5 Table-derived Operation 28
4.2 ARCHITECTURE 2: SIMULTANEOUS PROCESSING ARCHITECTURE 29
4.2.1 Horizontal Filtering Unit 31
4.2.2 Vertical Filtering Unit 32
4.2.3 Transposing Unit 33
4.2.4 Memory Interface 34
4.2.5 Parameter Interface 34
4.2.6 Control Unit 35
4.2.7 Data flow of SPA Architecture 35
4.3 ARCHITECTURE3:VERTICAL PROCESSING ARCHITECTURE 37
4.4 ARCHITECTURE4:PARALLEL PROCESSING ARCHITECTURE 39
4.5 ARCHITECTURE5:CONFIGURABLE WINDOW-BASED ARCHITECTURE 40
4.5.1 Basic Window Processing Approach 42
4.5.2 Advanced Window Processing Approach 47
4.5.3Window Architecture with Parallel Processing Engine 51
CHAPTER 5 PERFORMANCE EVALUATION 52
5.1 MEMORY PERFORMANCE 52
5.2 SYSTEM PERFORMANCE 53
5.3 IMPLEMENTATION 55
CHAPTER 6 CONCLUSIONS AND FUTURE WORK 57
6.1 CONCLUSIONS 57
6.2 FUTURE WORK 57
REFERENCES 59
BIOGRAPHY 64
PUBLICATION LIST 65

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