臺灣博碩士論文加值系統

電阻網路平均化技術可以有效的消減快閃式類比數位轉換器中比較器間的隨機偏移誤差值，但在電阻網路的邊界會產生非對稱的問題必須靠額外的電路解決，因此會造成更大的功率消耗以及信號範圍，自動歸零機制是另一有效抑制隨機偏移誤差的方法，但在連續信號轉換的應用上，要將一無空轉時間的自動歸零機制實現於一高速低潛伏的快閃式類比數位轉換器是相當困難的。在本論文，提出了一個具有單時脈相位的電容平均化技術來實現這個目標。電容平均化技術沒有邊界效應的限制，具有消減偏移誤差值的作用並因此縮小了第一級前置放大器的面積。又此技術是以自動歸零機制為主幹，故提出了一個開關式前置放大器來避免傳統自動歸零機制必須使用非重疊時脈相位的限制與消除高速自動歸零機制對輸入端的干擾。此外，相對於近年來所發表的自動歸零機制快閃式類比數位轉換器所需多相位時脈，所提出的技術具有單一相位控制的優點並避免了同步的問題。內插技術亦使用於此設計中，用來降低輸入負載前置放大器數目以及差值非線性誤差。
此類比數位轉換器之實現是採用0.18微米，1P6M互補型金氧半混合信號製程，面積為1.18微米平方。量測結果顯示此設計可以在500MHz的操作速度下，輸入信號頻率在100MHz以內時，約有大於30分貝的SNDR動態表現。整個晶片不包含輸出緩衝器共消耗了198mW的功率，其中類比電路供應1.8V的電壓而數位電路則是供應2.3V的電壓。

Averaging networks suppress the random offset efficiently between the comparators in flash ADCs, but it causes limitations at the averaging network boundaries. Although the effect can be resolved by additional terminal circuits, it costs larger power consumption and input headroom. Auto-zeroing technique is another effective way to reduce the error, but it is difficult to implement auto-zeroing without idle time in a high speed low latency flash for continuous data conversion. In this thesis, capacitor averaging with single-phase clock technique is proposed to achieve the target. Capacitor averaging technique without boundary limitation can alleviate random offset, and thus, reduce the area of first preamplifier stage. Since the technique is based on auto-zeroing technique, a switching preamplifier is provided to avoid non-overlap control signals requirement by conventional auto-zeroing ADCs and eliminate the interference caused by the high speed auto-zeroing operation at input nodes. Besides, the proposed technique has the merit of a single clock phase control to avoid synchronous issues since mutli-clock phase are necessary for recent published flash ADCs with auto-zeroing technique. Interpolation technique is also used in this design to reduce input loading, preamplifier number and differential nonlinearity (DNL) error in the ADC.
The ADC is fabricated in 0.18�慆 1P6M CMOS technology and occupies an area of 1.18mm2. The measurement results show that this design can achieve an operating rate of 500MHz with SNDR>30dB when input frequency < 100MHz. The total Chip draws 198mW non-including output buffer and the property runs off 1.8V analog and 2.3V digital supplies.

Table of Contents
1 Introduction...1
1.1 Motivation...1
1.2 Organization...2

2 Error Analysis of Flash ADC ...4
2.1 Quantization Error...4
2.2 Noise...7
2.3 Offset Mismatch...9
2.4 Clock Skew Effect...13
2.5 Signal Dependent Comparator Delay Error...16
2.6 Kickback Noise...20
2.7 Metastability and Hysteresis...21
2.8 Bubble Error...23

3 Proposed Technique of the Flash ADC...25
3.1 Interpolation Technique...25
3.1.1 Interpolation Typ...27
3.1.2 Interpolation Analysis...29
3.2 Auto-zeroing Technique...31
3.2.1 Auto-zeroing Principle...31
3.2.2 Auto-zeroing Topology...32
3.2.3 Modified Auto-zeroing...34
3.3 Averaging Technique...37
3.3.1 Resister Averaging Network...38
3.3.2 Offset Reduction with Averaging Network...40
3.3.3 Mathematic Derivation of Averaging Network...42
3.4 Reinterpolation Technique...45
3.5 Proposed Capacitor Averaging with Single-Phase Clock...47

4 Circuit Design of the Flash ADC...52
4.1 The Architecture of Proposed ADC...52
4.2 Reference Ladder Consideration...54
4.2.1 Effect to the Accuracy of Resistor Ladder...54
4.2.2 Matching Behavior of the Resistor Ladder...55
4.3 Front-End Track and Hold Circuit...57
4.4 Comparator Circuit Design...59
4.4.1 Circuit Topology and Consideration...60
4.4.2 Switching Preamplifier...61
4.4.3 Preamplifier2 Circuit...62
4.4.4 Latch Circuit...63
4.5 Digital Encoder Design...65
4.5.1 Consideration of Digital Encoder...66
4.5.2 Implementation of Digital Encoder...67
4.6 Timing Generator Circuit....68

5 Layout and Results...72
5.1 Power Supply Partition...72
5.2 Floor Plan and Layout...73
5.3 Measurement Considerations...74
5.3.1 Measure Step...75
5.4 PCB Design Consideration...76
5.4.1 Transmission Line Effect...76
5.4.2 Crosstalk...76
5.4.3 Decoupling...76
5.4.4 PCB Fabrication...77
5.5 Experimental Result...77

6 Conclusion and Future Work...82

Reference ...84

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