臺灣博碩士論文加值系統

本論文主要在設計應用在超寬頻頻率合成器的二個方塊電路，除三電路與四相位振盪器，最後再將兩個電路做整合，其製程皆採用0.18微米的互補式金氧半導體製程來設計。

除三電路是採用電流邏輯使其適用在高頻的操作，四相位振盪器的部份，相位雜訊為設計的主要考慮，因在傳統的架構裡，耦合電晶體(coupling transistor)和電流源是造成相位雜訊差的兩個主要原因，故傳統架構無法有良好的相位雜訊，所以此四相位振盪器藉著疊接方式的耦合電晶體和切換式電流源去做改善，並用電容去做7.128GHz和6.072GHz的切換，而除三電路與四相位振盪器整合的操作為先利用振盪器產生3.168GHz和4.224GHz的頻率後再用除三電路做除頻的動作。

此論文的貢獻為:在除三電路的利用CLK做為摺疊式轉導器的開關訊號切換電流鏡的電流，如此可使電晶體減少一個階層以降低操作電壓，而四相位振盪器的耦合電晶體採用疊接方式的架構後，使用切換式電流源仍可增加電路的效能，而整體的效能也比單獨使用一種上述的架構佳。

In this thesis, two function block circuits, including a divide-by-three circuit and a QVCO, are designed for UWB frequency synthesizer, and then integrate them together. All designs are based on 0.18um CMOS process.

The divider adopts current-mode logic to be suitable for operating at high frequency. Phase noise is the major consideration of design in our QVCO. The noises from the coupling transistors and the mirror current transistors are two major noise contributors in a traditional QVCO, so it can’t have good performance of phase noise. In our QVCO, we improve the performance by cascode coupling transistors and switching tail current sources and switch the oscillation frequency between 7.128GHz and 6.072GHz by switching the capacitor. The integration of divider and QVCO is to implement a QVCO that oscillates at 3.168GHz and 4.224GHz and then divide the output frequency by a divide-by-three circuit.

The contributions of this thesis are: we use the CLK signal to be the switch of mirror current by a folded transconductor stage so that it can decrease the stack number of transistors per branch to reduce the supply voltage. When cascade coupling transistors are used, it can further improve the performance of QVCO circuit by adopting switching tail current sources. And the entire performance of our QVCO is better than that of the oscillator which uses only one of the above-mentioned topologies.

Chapter 1 Introduction....................................1
1.1 Introduction of UWB...................................1
1.2 Motivation............................................4
1.3 Thesis Organization...................................9

Chapter 2 Introduction of Divider........................11
2.1 Introduction.........................................11
2.2 Major topologies of Frequency Dividers...............12
2.2.1 Static Flip-Flops Frequency Divider...............12
2.2.2 Dynamic Flip-Flops Frequency Divider..............13
2.2.3 Injection locked Frequency Divider................14
2.2.4 Regenerative Frequency Divider....................16
2.3 Comparison and Conclusion of Frequency Dividers......17

Chapter 3 Principles of VCO..............................19
3.1 Passive Components...................................19
3.1.1 Varactor..........................................19
3.1.2 Inductor..........................................23
3.1.3 LC-Tank...........................................27
3.2 Basic Theorems of VCO................................29
3.2.1 Positive Feedback Analysis........................29
3.2.2 LC-VCO Architecture................................30
3.2.3 Comparison of Different LC-Tank VCO Architectures.32
3.2.4 Four Methods to Generate Quadrature...............34
3.3 Characteristics of VCO...............................40
3.3.1 Phase Noise.......................................40
3.3.2 Tuning Range.......................................42
3.3.3 Quality Factor....................................43
3.3.4 Pushing Effect....................................44
3.3.5 Pulling Effect....................................45
3.3.6 Temperature Noise.................................45
3.3.7 Harmonic Distortion...............................45

Chapter 4 Design of QVCO and Divider.....................47
4.1 Design of Divider....................................47
4.1.1 Architecture of Core Circuit......................47
4.1.2 Buffer Stage......................................50
4.1.3 Layout of Divide-by-three Circuit.................51
4.2 Design of QVCO.......................................51
4.2.1 Architecture of Core QVCO.........................52
4.2.2 Buffer Stage......................................55
4.2.3 Switched Capacitor Array..........................56
4.2.4 Layout of QVCO....................................57
4.3 Design of Integration of QVCO and Divider............58
4.3.1 Architecture of Integration of QVCO and Divider...58
4.3.2 Layout of Integration of QVCO and Divider.........59

Chapter 5 Post-Simulation Results........................61
5.1 Simulation of Divider................................61
5.2 Simulation of QVCO...................................63
5.2.1 Tuning Range......................................63
5.2.2 Phase Noise.......................................65
5.2.3 Transient Response and Spectrum...................70
5.2.4 Comparison with Other VCOs........................72
5.3 Simulation of Integration of QVCO and Divider........73

Chapter 6 Measurement Results............................81
6.1 Measurement of Divider...............................81
6.2 Measurement of QVCO..................................85
6.3 Measurement Discussion...............................89

Chapter 7 Conclusion and Future Work.....................91
7.1 Conclusion...........................................91
7.2 Future Work..........................................93

Reference................................................95

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