臺灣博碩士論文加值系統

生物辨識是近年來最熱門的研究議題，而其中最可靠的就是採用指紋辨識。電容式指紋感測器的原理，是藉由量測感測電極板與指紋表面紋路的深淺距離不同，而造成的電容值變化，以此擷取出指紋影像。
在本論文中，我們將會討論低寄生電容與低功率CMOS電容式指紋感測器之研製。藉由新的感測器單元電路佈局安排方法，可以消除寄生電容的影響，並且採用最小尺寸的MOS開關以減少MOS開關的非理想效應，以及獲得良好的電容對電壓轉換特性。而功率消耗方面，則透過控制感測讀取電路中緩衝放大器的靜態消耗電流，以節省功率消耗。
我們採用國家晶片系統設計中心提供的TSMC 0.35μm Mixed-Signal 2P4M CMOS製程，完成32乘32陣列的指紋感測器晶片實作，包含了感測器陣列和周邊控制電路，以及類比至數位轉換器，晶片整體面積為1900μm × 2570μm。晶片工作電壓為3.3V，時脈速度為4MHz。感測電容範圍為0fF至60fF，對應的類比輸出電壓為3.02V至1.57V，以及六位元的數位輸出。晶片整體消耗功率小於5.5mW。

In recent years, Biometric Identification has become the most popular research topic, and one of the most robust methods is fingerprint identification. A capacitive fingerprint sensor acquires the fingerprint image by measuring capacitance variation,
caused by different distance between sensing electrode and fingerprint surface.
In this thesis, we present a low parasitic capacitance and low-power CMOS Capacitive Fingerprint Sensor Readout Circuit. The effect of parasitic capacitance has been eliminated with novel layout structure in sensor cell, and minimal size switch is used in readout circuit to avoid non-ideal effect of MOS switch and to achieve good C-V characteristic. Power consumption is reduced with quiescent current control in
buffer amplifier of readout circuit.
A 32x32 fingerprint sensor array is implemented in TSMC 0.35μm Mixed- Signal 2P4M CMOS technology provided by Chip Implementation Center. Including the sensor array, peripheral control circuits and analog to digital converter, the chip area is 1900μm × 2570μm. The chip works at 3.3V power supply and operates at 4MHz clock rate. Capacitance value from 0fF to 60fF can be sensed, corresponding analog output voltage is from 3.02V to 1.57V and the digital output is 6 bits. The
overall power consumption is less than 5.5mW.

誌謝
中文摘要.................................................... I
英文摘要.................................................... II
目錄........................................................ III
圖目錄...................................................... V
表目錄...................................................... IX

第一章 緒論................................................ 1
1.1 研究動機.......................................... 1
1.2 研究背景.......................................... 2
1.3 論文組織架構...................................... 3

第二章 指紋感測系統........................................ 4
2.1 指紋感測系統簡介.................................. 4
2.1.1 指紋特徵簡介............................. 4
2.1.2 指紋感測系統............................. 5
2.1.3 指紋感測系統之感測讀取電路架構........... 6
2.1.4 指紋感測器陣列架構....................... 7
2.2 指紋感測器分類與簡介.............................. 10
2.3 電容式指紋感測讀取電路分析........................ 14
2.4 非理想效應考量.................................... 23
2.4.1 寄生電容效應............................. 23
2.4.2 開關非理想效應........................... 23
2.4.3 製程參數變異效應......................... 25

第三章 電容式指紋感測器設計................................ 26
3.1 低寄生電容感測器單元設計.......................... 26
3.2 感測器陣列設計.................................... 29
3.3 電容式指紋感測讀取電路............................ 30
3.3.1 感測讀取電路設計......................... 30
3.3.2 非理想效應討論........................... 32
3.3.3 感測讀取電路模擬......................... 36
3.3.4 感測讀取電路與感測器單元整體設計、佈局與模擬.......................................
42
3.4 數位控制電路...................................... 47
3.4.1 數位控制電路架構......................... 47
3.4.2 行與列選擇移位暫存器電路設計............. 48
3.4.3 數位控制電路模擬......................... 50
3.5 六位元逐漸逼近式類比至數位轉換器.................. 52
3.5.1 六位元逐漸逼近式類比至數位轉換器架構..... 52
3.5.2 六位元逐漸逼近式類比至數位轉換器模擬..... 55
3.5.3 六位元逐漸逼近式類比至數位轉換器佈局..... 59
3.6 32乘32低功率感測讀取電路陣列..................... 62


3.6.1 32乘32低功率感測讀取電路陣列架構......... 62
3.6.2 32乘32低功率感測讀取電路陣列模擬......... 64
3.6.3 32乘32低功率感測讀取電路陣列佈局......... 69

第四章 電容式指紋感測器量測............................ 72
4.1 測試環境配置圖與晶片照相圖........................ 72
4.1.1 測試環境配置圖........................... 72
4.1.2 晶片照相圖............................... 73
4.2 32乘32感測讀取電路陣列量測結果................... 74
4.2.1 讀取畫面結束訊號量測結果............. 74
4.2.2 不均勻現象量測結果....................... 75
4.2.3 類比與數位輸出量測結果................... 76
4.2.4 指紋實際量測結果......................... 77
4.2.5 量測結果討論............................. 80

第五章 結論................................................ 81

參考文獻.................................................... 82

[1]C. Tsikos, “Capacitive Fingerprint Sensor,” U.S. Patent 4,353,056, Oct. 5, 1982.
[2]Anderson S, Bruce W.H., Denyer P.B., Renshaw D, Wang G, “A single chip sensor and image processor for fingerprint verification,” IEEE Proceedings of the Custom Integrated Circuits Conference, pp. 12.1/1－12.1/4, 1991.
[3]A.G. Knapp, “Fingerprint sensing device and recognition system having predetermined electrode activation,” U.S. Patent 5,325,442, Jun. 28, 1994.
[4]N. Young, G. Harkin, R. Bunn, D. McCulloch, R. Wilks, and A. Knapp, “Novel fingerprint scanning arrays using polysilicon TFT’s on glass and polymer substrates,” IEEE Electron Device Letter, Vol. 18, pp. 19–20, Jan. 1997.
[5]R. Guerrieri and M. Tartagni, “A fingerprint sensor based on the feedback capacitive sensing scheme,” IEEE Journal of Solid-State Circuits, Vol. 33, pp. 133–142, Jan. 1998.
[6]D. Inglis, L. Manchanda, R. Comizzoli, A. Dickinson, E. Martin, S. Mendis, P. Silverman, G. Weber, B. Ackland, and L. O’Gorman, “A robust, 1.8 V 250μW direct-contact 500 dpi fingerprint sensor,” in ISSCC Digest of Technical Papers, pp. 284–285, Feb. 1998.
[7]S. Shigematsu, H. Morimura, Y. Tanabe, and K. Machida, “A 15×15 mm2 single-chip fingerprint sensor and identifier using pixel parallel processing,” in ISSCC Digest of Technical Papers, pp. 138–139, Feb. 1999.
[8]Jeong-Woo Lee, et al., “A 600-dpi Capacitive Fingerprint Sensor Chip and Image-Synthesis Technique,” IEEE Journal of Solid State Circuits, Vol. 34, pp. 469-475, Apr. 1999.
[9]S. Jung, R. Thewes, T. Scheiter, K. Goser, and W.Weber, “A low-power and high-performance CMOS fingerprint sensing and encoding architecture,” IEEE Journal of Solid-State Circuits, Vol. 34, pp. 978–984, Jul. 1999.
[10]N. Manaresi, R. Rambaldi, M. Tartagni, Z. M. K. Vajna and R. Guerrieri, “ A CMOS-only micro touch pointer,” IEEE Journal of Solid-State Circuits, Vol. 34, pp. 1860–1868, Dec. 1999.
[11]S. Shigematsu, H. Morimura, Y. Tanabe, T. Adachi, and K. Machida, “A single-chip fingerprint sensor and identifier,” IEEE Journal of Solid-State Circuits, Vol. 34, pp. 1852–1859, Dec. 1999.
[12]S. Jung, et al., “CMOS Fingerprint sensor with automatic contrast adjustment and pixel-parallel encoding logic,” VLSI Circuits Symposium, pp. 161-164, 1999.
[13]Ji-Song Han, Kadowaki T., Sato K., Shikida M., “Thermal analysis of fingerprint sensor having a microheater array,” Proceedings of Micromechatronics and Human Science, pp. 199-205, 1999.
[14]S. Jung, “Capacitive CMOS Fingerprint Sensor with On-Chip Parallel Signal Processing,” PhD. Thesis, Department of Microelectronics, University of Dortmund, Dortmund, Germany, pp. 16, Jan. 2000.
[15]H. Morimura, S. Shigematsu, and K. Machida, “A novel sensor cell architecture and sensing circuit scheme for capacitive fingerprint sensors,” IEEE Journal of Solid-State Circuits, Vol. 35, pp. 724–731, May 2000.
[16]H. Morimura, S. Shigematsu, T. Shimamura, K. Machida, and H. Kyuragi, “A pixel-level automatic calibration circuit scheme for sensing initialization of a capacitive fingerprint sensor LSI,” in Symp. VLSI Circuits Digest of Technical Papers, pp. 171–174, Jun. 2001.
[17]K. Machida, S. Shigematsu, H. Morimura, Y. Tanabe, N. Sato, N. Shimoyama, T. Kumazaki, K. Kudou, M. Yano, and H. Kyuragi,“ A novel semiconductor capacitive sensor for a single-chip fingerprint sensor/identifier LSI,” IEEE Transactions on Electron Devices, Vol. 48, pp.2273–2278, Oct. 2001.
[18]Kwang-Hyun Lee and Euisik Yoon, “A 500 dpi capacitive-type CMOS fingerprint sensor with pixel-level adaptive image enhancement scheme, ”in ISSCC Digest of Technical Papers, Vol 2, pp. 282–283, Feb. 2002.
[19]H. Morimura, S. Shigematsu, T. Shimamura, K. Machida and H. Kyuragi, “A Pixel-Level Automatic Calibration Circuit Scheme for Capacitive Fingerprint Sensor LSIs,” IEEE Journal of Solid-State Circuits, Vol. 37, pp. Oct. 2002.
[20]Giovanni Gozzini, “Capacitive Finger Detection for Fingerprint Sensor,” U.S. Patent 6,501,284 B1, Dec. 31, 2002
[21]R. Hashido, A. Suzuki, A. Iwata, T. Okamoto, Y. Satoh, M. Inoue, “A capacitive fingerprint sensor chip using low-temperature poly-Si TFTs on a glass substrate and a novel and unique sensing method,” IEEE Journal of Solid-State Circuits, Vol. 38, pp. 274－280, Feb. 2003.
[22]Sato N, Machida K, Morimura H, Shigematsu S, Kudou K, Yano M, Kyuragi H, “MEMS fingerprint sensor immune to various finger surface conditions,” IEEE Transactions on Electron Devices, Vol 50, Issue 4, pp. 1109 – 1116, Apr. 2003.
[23]Giovanni Gozzini, “Capacitive Pixel for Fingerprint Sensor,” U.S. Patent 6,636,053 B1, Oct. 21, 2003.
[24]Motoyasu Yano, Masashi Takeda, Takeshi Koyama, Shinozaki, “Capacitive Detecting Apparatus and Its Inspecting Method and Fingerprint Checking Apparatus,” U.S. Patent 6,681,033 B1, Jan. 20, 2004.
[25]H. Morimura, T. Shimannura, K. Fujii, S. Shigematsu,Y. Okazaki, M. Katsuyuki, “A zero-sink-current Schmitt trigger and window-flexible counting circuit for fingerprint sensor/identifier,” in ISSCC Digest of Technical Papers, Vol 1, pp. 122–517, Feb. 2004.
[26]Charlot B, Parrain F, Galy N, Basrour S, Courtois B, “A sweeping mode integrated fingerprint sensor with 256 tactile microbeams,” Journal of Microelectromechanical Systems, Vol 13, Issue 4, pp. 636 – 644, Aug. 2004.
[27]Meng-Lieh Sheu, Chih-Kuan Lai, Wei-Hung Hsu, Hong-Ming Yang, “A Novel Capacitive Sensing Scheme for Fingerprint Acquisition,” IEEE Conference on Electron Devices and Solid-State Circuits, pp. 627 – 630, 2005.
[28]Seung-Min Jung, Jin-Moon Nam, Dong-Hoon Yang, Moon-Key Lee, “A CMOS integrated capacitive fingerprint sensor with 32b microcontroller ,” in ISSCC Digest of Technical Papers, Vol 1, pp. 252 – 596, Feb. 2005.
[29]Seong-Jin Kim, Kwang-Hyun Lee, Sang-Wook Han, Euisik Yoon, “A 200x160 pixel CMOS fingerprint recognition soc with adaptable column-parallel processors,” in ISSCC Digest of Technical Papers, Vol 1, pp. 250 – 596, Feb. 2005.
[30]Sato N, Shigematsu S, Morimura H, Yano M, Kudou K, Kamei T, Machida K, “Novel surface structure and its fabrication process for MEMS fingerprint sensor,” IEEE Transactions on Electron Devices, Vol 52, Issue 5, pp. 1026 – 1032, May. 2005.
[31]Seung-Min Jung, Jin-Moon Nam, Dong-Hoon Yang, Moon-Key Lee, “A CMOS integrated capacitive fingerprint sensor with 32-bit RISC microcontroller,” IEEE Journal of Solid-State Circuits, Vol. 40, pp. 1745－1750, Aug. 2005.
[32]Meng-Lieh Sheu,Yu-Sheng Tiao, Wen-Fu Yang, Hong-Ming Yang, “A Sweeping Mode CMOS Capacitive Fingerprint Sensor Chip,” in International Computer Symposiums , 2006.
[33]Galy N, Charlot B, Courtois B, “A Full Fingerprint Verification System for a Single-Line Sweep Sensor,” IEEE Sensors Journal, Vol 7, Issue 7, pp. 1054–1065, Jul. 2007.