跳到主要內容

臺灣博碩士論文加值系統

(3.235.227.117) 您好!臺灣時間:2021/08/01 21:46
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

: 
twitterline
研究生:張銘哲
研究生(外文):Ming-Che Chang
論文名稱:暫存器陣列式快速傅立葉轉換處理器之超大型積體電路設計
論文名稱(外文):VLSI Design of Register Array Based Fast Fourier Transform Processor
指導教授:吳俊德吳俊德引用關係
指導教授(外文):Gin-Der Wu
學位類別:碩士
校院名稱:國立暨南國際大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:英文
論文頁數:66
中文關鍵詞:快速傅立葉轉換語音信號辨識數位信號處理器
外文關鍵詞:fast Fourier transformspeech recognitiondigital signal process processor
相關次數:
  • 被引用被引用:0
  • 點閱點閱:128
  • 評分評分:
  • 下載下載:23
  • 收藏至我的研究室書目清單書目收藏:0
本篇論文提出一顆具有快速傅立葉轉換處理器的晶片,專門應用於語音信號辨識之使用。這個系統主要包含個主要的部份,分別是快速傅立葉轉換(fast Fourier transform)處理器、梅爾倒頻譜參數(Mel-scale frequency cepstral coefficient)擷取晶片以及算數邏輯運算單元(ALU)架構的數位信號處理器。其中數位信號處理器和梅爾倒頻譜參數擷取晶片已經被之前的學長所實現,在這篇論文我們採用一種新的暫存器陣列方法並使用radix-22管線式的架構來設計,為了降低晶片的功率消耗以及計算量。最後此晶片應用TSMC 0.18um 標準單元(standard cell)合成出處理器電路,FFT/IFFT處理器Gate count約為196172,而latency 時間約為2.56μs,工作頻率為100MHz。
This paper proposed the chip design of speech recognition for multimedia system. It is composed by three cores: a register array based fast Fourier transform (FFT) processor, a Mel-scale frequency cepstral coefficient (MFCC) circuit, and a dual-ALU digital signal process (DSP) processor with dynamic time warping speech recognition algorithm. The DSP processor and MFCC processor had been implemented by previous researcher. In this FFT processor, we proposed a novel register array based pipelined radix-22 structure to reduce power consumption and computation cycles. The chips are synthesized by TSMC 0.18um cell library. The gate count of the FFT chip is about 196172. The latency is about 2.56μs. The FFT chip is work at 100 MHz.
Contents

Acknowledgement
Chinese abstract i
English abstract ii
Contents iii
List of tables v
List of figures vi

1. Introduction 1
1.1 Preview of the FFT/IFFT processor 1
1.2 Organization of This Thesis 4
2. Overview of the System 5
2.1 Introduction 5
2.2 DTW algorithm 7
2.3 Preview of the DSP processor 10
2.4 Preview of our proposed dual-ALU DSP processor 11
2.5 Preview of the MFCC chip 18
3. Fast Fourier Transform algorithms 28
3.1 Introduction 28
3.2 Radix-2 FFT Algorithm 29
3.3 Radix-4 FFT Algorithm 31
3.4 Radix-22 FFT Algorithm 32
3.5 Summary 33
4. Chip design of FFT/IFFT 34
4.1 Introduction 34
4.2 Block Diagram of the FFT Processor 35
4.3 Hardware architecture of the butterfly unit 36
4.4 Hardware architecture of the register array 40
4.5 Hardware architecture of the address generator 43
4.6 Hardware architecture of the control unit 46
4.7 Summary of FFT circuit 48
5. Analysis 49
6. Conclusion 53

Bibliography 54
[1]L. R. Rabiner and B. Gold, “Theory and Application of Digital Processing.” Prentice-Hall, Inc, 1975.
[2]E. H. Wold and A. M. Despain, “Pipeline and parallel-pipeline FFT Processor for VLSI Implementation,” IEEE Trans.Comput., C-33(5):414-426, May, 1984.
[3]M. B. Bevan, “A Low-Power, High-Performance,1024-point FFT Processor,” IEEE Journal of Solid-State Circuits, vol. 34, no. 3, pp. 380-387, March, 1999.
[4]L. Jia, Y. Gao, J. Isoaho, and H. Tenhunen, “Implementation of a low power 128-point FFT Processor,” in Proceedings of Fifth International conference on Solid-State and Integrated Circuit Technology, pp. 369-372, 1998.
[5]K. S. Stevens and B. W. Suter, “A mathematical approach to a low power FFT Architecture,” in Proc. IEEE International Symposium on Circuits and Systems, pp. II-21-II-24, 1998.
[6]M. Hasan, T. Arslan, and J. S. Thompson, “A delay spread based low power reconfigurable FFT processor architecture for wireless receiver,” IEEE International Symposium on System-on-Chip, pp. 135-138, 2003.
[7]Yutian Zhao, Ahmet T. Erdogan, and Tughrul Arslan, “A Low-Power and Domain-Specific Reconfigurable FFT Fabric for System-on-Chip Applications,” IEEE International Symposium on Parallel and Distributed, pp. 169a-169a, April, Nov. 2005.
[8] G. Bi and E. V. Jones, “A pipelined A pipelined FFT processor for word-sequential data, ” IEEE Trans. Acoust., Speech, Signal Processing,
37(12):1982-1985, Dec. 1989.
[9] H. Sakoe and S. Chiba, “Dynamic programming algorithm optimization for spoken word recognition,” IEEE Trans. Acoustics, Speech, and Signal Processing, vol. 26. pp. 43-49, Feb 1978.
[10] H. F. Silverman and D. P. Morgan, “The application of dynamic programming to connected speech recognition,” IEEE ASSP Magazine, vol. 7, pp. 6-25, July 1990.
[11] L. Rabiner, A. Rosenberg, and S. Levinson, “Conderations in dynamic time warping algorithms for discrete word recognition” IEEE Trans. Acoustics, Speech, and Signal Processing, vol. 26. pp. 575-582, Dec 1978.
[12] Wang Jia-Ching, Wang Jhing-Fa, and Weng Yu-Sheng, “Chip Design of Mel Frequency Cepstrum Coefficient for Speech Recognition,” IEEE Trans. Acoustics, Speech, and Signal Processing, vol. 6, pp. 3658-3661, June 2000.
[13] H. Hassler and N. Takagi, “Function Evalution by Table Look-up and Address,” Proceeding of the 12th Symposium on Computer Arithmeti, pp. 10-16 c,1997.
[14] J. W. Cooley and J. W. Tukey, “An algorithm for the machine calculation of complex Fourier series,” Math. Comp., vol. 19, pp.297-301, April 1965.

[15] Yeh Wen-Chang and Jen Chein-Wei, “High-speed and low-power split-radix FFT”, Signal Processing, IEEE Transactions on [see also Acoustics, Speech, and Signal Processing, IEEE Transactions on, Volume 51, Issue 3, March 2003 Page(s):864 – 874 Digital Object Identifier10.1109/TSP. 2002.806904

[16] Logic Synthesis with Design Compiler, Inc. January 2006.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top