臺灣博碩士論文加值系統

本研究致力於不需負載電容及寬穩定度範圍和快速暫態切換特性之低壓降線性穩壓器(LDO Regulator)的實現。我們提出兩個全新的頻率補償架構於穩壓器電路。本論文提供系統晶片(System on a Chip，簡稱SoC)或可攜式產品的電源管理系統可以完全移除晶片外部大體積電容的解決方法。
首先，設計增強型主動回授補償技術去加強頻率響應。此低壓降線性穩壓器從負載電流0 mA至100 mA範圍內，在沒有負載電容的情況下仍然可以提供高穩定度，或是當LDO穩壓器外部有負載電容時，其等效串聯電阻(Equivalent Series Resistor, ESR)可以有較寬範圍的設計值。而且，此技術僅需兩個很小的補償電容，這樣可以讓我們輕易地將補償電容整合到LDO穩壓器晶片內部。所設計的系統輸出電壓為1.5 V，最大可承受負載電流為100 mA。
最後，提出一個精簡型CMOS參考電壓源利用臨界電壓和遷移率溫度係數相互補償並使用基底電位微調技術。所設計的參考電壓源具有低溫度係數(≈ 14 ppm/℃)，而且最小的供應電壓為一伏特。在沒有濾波電容情況下，低頻時的電源拒斥比大於 60 dB。本論文所呈現之晶片都是使用台積電0.35微米2P4M 標準互補式金氧半製程來作設計。

The research focuses on the realization of cap-less, wide stable range, and fast transient low dropout (LDO) linear regulator. We present two novel frequency compensation architecture for LDO circuit. The thesis provides a solution for power management system of portable devices. It can also be embedded in SoC (System on a Chip) to fully remove bulky external capacitors.
First, an enhanced active feedback frequency compensation technique is employed to improve its frequency response. This LDO can provide high stability for loading current from 0 mA to 100 mA without loading capacitors or with loading capacitors which have wide range ESR (equivalent series resistance). Moreover, this technique only requires two small compensation capacitors. This allows us to integrate the compensation capacitors within the LDO chip easily. The system has an output voltage of 1.5 V and a maximum current capability of 100 mA.
Finally, a compact CMOS voltage reference based on the mutual compensation of threshold voltage and mobility temperature coefficients with body potential trimming technique is presented. This voltage reference has a low temperature coefficient (≈ 14 ppm/℃), and the minimum supply voltage is 1V. The power supply rejection ratio without any filtering capacitor at low frequency are larger than 60 dB. The proposed chips in this thesis were fabricated using a standard TSMC 0.35 μm 2P4M CMOS process.

中文摘要 i
英文摘要 ii
誌謝 iv
目錄 v
圖目錄 viii
表目錄 xiv
Chapter 1 緒論 1
1.1 研究背景 1
1.2 研究動機 2
1.3 論文架構 3

Chapter 2 低壓降線性穩壓器的基礎 4
2.1 低壓降線性穩壓器之簡介與應用 4
2.2 規格與特性 6
2.2.1 輸出電壓差(Dropout Voltage) 6
2.2.2 負載穩壓(Load Regulation) 6
2.2.3 線上穩壓(Line Regulation) 7
2.2.4 暫態響應(Transient Response) 8
2.2.5 靜態電流(Quiescent Current) 10
2.2.6 效率(Efficiency) 11
2.2.7 電源拒斥比(Power Supply Rejection Ratio) 11
2.2.8 輸出雜訊(Output Noise) 12
2.2.9 電壓精確度(Voltage Accuracy) 12
2.3 低壓降線性穩壓器電路設計的相關考量 14
2.4 傳統低壓降線性穩壓器的頻率響應及穩定度分析 16
2.5 文獻回顧 19

Chapter 3 具有高穩定度與高精確度之低壓降線性穩壓器 21
3.1 提出新的低壓降線性穩壓器之補償技術 21
3.1.1 電路架構 21
3.1.2 頻率響應與小訊號分析 22
3.1.3 模擬迴路增益的方法 26
3.1.4 穩壓器內部雜訊分析 27
3.2 模擬結果 29
3.3 晶片佈局圖與電路板 37
3.4 實驗結果 38
3.4.1 測試考量 38
3.4.2 量測結果 39

Chapter 4 具有強健的頻率補償且不需外部電容之低壓降線性穩壓器 45
4.1 提出新的低壓降線性穩壓器之補償技術 45
4.1.1 電路架構 45
4.1.2 頻率響應與小訊號分析 47
4.2 模擬結果 50
4.3 晶片佈局圖與電路板 60
4.4 實驗結果 61
4.4.1 測試考量 61
4.4.2 量測結果 62

Chapter 5 可操作於一伏特供應電壓且溫度係數14ppm/℃之參考電壓源 69
5.1 簡介 69
5.2 參考電壓源基本操作原理 69
5.2.1 負溫度係數電壓 69
5.2.2 正溫度係數電壓 70
5.2.3 傳統的帶差參考電路 70
5.3 文獻回顧 71
5.4 研究動機 75
5.5 設計新的參考電壓源 75
5.5.1 電路架構 75
5.5.2 操作原理與理論分析 76
5.6 模擬結果 78
5.7 晶片佈局圖與電路板 84
5.8 實驗結果 85
5.8.1 測試考量 85
5.8.2 量測結果 86

Chapter 6 結論 89

參考文獻 91

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