臺灣博碩士論文加值系統

隨著各種多媒體視訊標準的發展,越來越多人努力設計可支援多視訊標準的系統單晶片。MPEG在2004年時成立了一個小組,希望可以設計出有彈性的多媒體視訊系統。本篇論文設計一系統單晶片架構可支援MPEG所提出的系統

Due to the variety of popular video coding standards, many efforts have been put into the design of a single video decoder chip that supports multiple formats. In 2004, ISO/IEC MPEG started a new work item to facilitate multi-format video codec design and to enable more flexible usage of coding tools. The work item has turned into the MPEG Reconfigurable Video Coding (RVC) framework. The key concept of the RVC framework is to allow flexible reconfiguration of coding tools to create different codec solutions on-the-fly. In this thesis, flexible SoC architecture is proposed to support the RVC framework. Some analysis has been conducted to show the extra costs required for this platform compared to hard-wired codec architecture. In conclusion, the RVC framework can be mapped to an SoC platform to provide flexibility and scalability for dynamic application environment with reasonable cost in hardware design.

1. Introduction 14
1.1 Introduction to MPEG RVC Framework 15
2. Previous Works 19
2.1 Traditional ASIC design approach 19
2.2 SoC architecture for multimedia system 20
2.3 Reconfigurable video coding 21
2.3.1 RVC Proposal from Hanyang University 22
3. Proposed RVC Framework 26
3.1 SoC architecture of the propose RVC framework 26
3.2 Propose RVC framwrok 28
3.2.1 Design of Global Control Unit 29
3.2.2 Memory allocator 32
3.3 Implementation of FUs in the propose RVC framework 34
4. Design of hardware functional units 35
4.1 Introduction to H.264/AVC decoding 35
4.2 Design of inverse transform and inverse quantizer 37
4.2.1 Architecture of inverse integer transform 38
4.2.2 Architecture of the 4x4 inverse hadamard transform 40
4.2.3 Architecture of the inverse quantizer 42
4.3 Design of intra compensation 43
4.3.1 Intra prediction 43
4.3.2 Proposed architecture of intra compensation 45
4.3.3 Eight directions of I4MB mode 45
4.3.4 DC mode for I4MB mode and I16MB 50
5. Experimental results 52
5.1 Emulation platform 52
5.1.1 Integration board (Arm integrator/AP) 53
5.1.2 Core module (CM) 53
5.1.3 Logic module (LM) 54
5.1.4 memory map for arm integrator 55
5.2 Synthesis report for hardware functional units 56
5.3 Performance analysis 57
6. Conclusion and Future work 59
7. Reference 61

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