臺灣博碩士論文加值系統

隨著矽製程的發展，我們能夠在單一個晶片中放置越來越多的電路。這代表了越進步的設計將需要越多的輸入輸出訊號。覆晶封裝方式是IBM在1960年代所發展出來的，它比典型的周邊打線接合方式在輸出入訊號上能提供更多的個數，覆晶設計其中一個最重要的特性就是輸出入緩衝器可以像核心電路一樣放在晶片內的任何一個地方。在這邊論文裡，我們發展了一個在覆晶設計時，核心區塊與輸出入緩衝器擺置的演算法並且同時考量接線長度、訊號歪斜與電源完整性.

As silicon technology scales, we can integrate more and more circuits on a single chip,which means more I/Os are needed in modern designs. The flip-chip packaging was developed by IBM in 1960's. It is better than the typical peripheral wire-bond design in the increase in I/O count. One of the most important characteristics of flip-chip designs is that the input and output buffers could be placed anywhere inside a chip, like core cells. In this thesis, we develop an block and I/O buffer placement algorithm in wire length and signal skew optimization and power integrity concerning for flip-chip design.

1 Introduction 1
1.1 Our Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Organization of this Thesis . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Preliminaries 5
2.1 Flip-Chip Design Constraints . . . . . . . . . . . . . . . . . . . . . . 5
2.1.1 Skew and Path Delay Constraints . . . . . . . . . . . . . . . . 5
2.1.2 Differential Pair Constraint . . . . . . . . . . . . . . . . . . . 7
2.1.3 Power Integrity Constraint . . . . . . . . . . . . . . . . . . . . 7
2.2 Previous Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.1 Simultaneous Block and I/O Buffer Floorplanning for Flip-
Chip Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.2 Constraint Driven I/O Planning and Placement for Chip-package
Co-design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.3 I/O Buffer Placement Methodology for ASICs . . . . . . . . . 9
2.3 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Proposed Methodology 11
iii
3.1 Block Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Buffer Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 Experimental Results 17
5 Conclusion and Future Work 21
Bibliography 22

[1] Chih-Yang Peng, Wen-Chang Chao, Yao-Wen Chang, , and Jyh-Herng Wang.“Simultaneous Block and I/O Buffer Floorplanning for Flip-Chip Design.”. In Asia and South Pacific Conference on Design Automation., pages 24–27, 2006.
[2] Faraday Corp. “Block and Input/Output Buffer Placement for Skew/Delay Minimization in Flip-chip Design”. In Proc. of ACM International Symposium on Physical Design. IC/CAD Contest,Taiwan, 2003. http :
//www:cs:nthu:edu:tw/ cad/cad91/Problems/P3/CADcontest2003P 3.pdf.
[3] Hao-Yueh Hsieh and Ting-Chi Wang. “Simple Yet Effective Algorithms for Block and I/O Buffer Placement in Flip-Chip Design*”. In IEEE International Symposium on Circuits and Systems, pages 1879 – 1882, 2005.
[4] Hung-Ming Chen, I-Min Liu, Muzhou Shao, Martin D.F. Wong, and Li-Da Huang. “I/O clustering in design cost and performance optimization for flipchip design”. In Proceedings. IEEE International Conference on Computer
Design, pages 562 – 567, 2004.
[5] Jinjun Xiong, Yiu-Chung Wong, Egino Sarto, and Lei He. “Constraint Driven I/O Planning and Placement for Chip-package Co-design”. In Asia and South
Pacific Conference on Design Automation,, 2006.
[6] J. N. Kozhaya, S. R. Nassif, and F. N. Najm. “I/O Buffer Placement Methodology
for ASICs”. In IEEE International Conf. on Electronic, Circuits and Systems, pages 245–248, 2001.
[7] Audet Jean, D.P. O’Connor, Mike Grinberg, and James P. Libous. “Effect of organic package core via pitch reduction on power distribution performance”.
In Proceedings Electronic Components and Technology Conference, pages 1449–1453, 2004.
[8] G. Yasar, C. Chiu, R.A. Proctor, , and J.P. Libous. “I/O Cell Placement and Electrical Checking Methodology for ASICs with Peripheral I/Os”. In IEEE International Symposium on Quality Electronic Design, pages 71 – 75, 2001.
[9] P.H. Buffet, J. Natonio, R.A. Proctor, Y.H. Sun, , and G. Yasar. “Methodology for I/O cell Placement and Checking in ASIC Designs Using Area-Array Power
Grid”. In IEEE Custom Integrated Circuits Conference, pages 125–128, 2000.
[10] R. Farbarik, X. Liu, M. Rossman, P. Parakh, T. Basso, , and R. Brown. “CAD Tools for Area-Distributed I/O Pad Packaging”. In IEEE Multi-Chip Module Conference, pages 125–129, 1997.
[11] P.S. Zuchowski, J.H. Panner, D.W. Stout, J.M. Adams, F. Chan, P.E. Dunn, A.D. Huber, , and J.J. Oler. “I/O Impedance Matching Algorithm for High Performance ASICs,”. In IEEE International ASIC Conference and Exhibit,
pages 270–273, 1997.
[12] C. Tan, D. Bouldin, , and P. Dehkordi. “Design Implementation of Intrinsic Area Array ICs”. In Proceedings 17th Conference on Advanced Research in
VLSI,, pages 82–93, 1997.
[13] R.J. Lomax, R.B. Brown, M. Nanua, , and T.D. Strong. “Area I/O Flip-Chip Packaging to Minimize Interconnect Length,”. In IEEE Multi-Chip Module Conference,, pages 2–7, 1997.
[14] S. N. Adya, I. L. Markov, , and P. G. Villarrubia. “On whitespace in mixed-size placement and physical synthesis”. In Proceedings of IEEE/ACM Int. Conf. on
Computer-Aided Design, pages 311–318, 2003.
[15] A. R. Agnihotri, M. C. Yildiz, A. Khatkhate, A. Mathur, S. Ono, and P. H. Madden. “Fractical cut: improved recursive bisection placement”. In Proceedings
of IEEE/ACM Int. Conf. on Computer-Aided Design,, pages 307–310,2003.
[16] A. E. Caldwell, A. B. Kahng, and I. L. Markov. “Can recursive bisection alone produce routable placement?”. In Proc. of ACM/IEEE Design Automation Conf., pages 477–482, 2000.
[17] T. Chan, J. Cong, and K. Sze. “Multilevel generalized force-directed method
for circuit placement”. In Proc. of ACM International Symposium on Physical
Design, 2005.