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研究生:葉志益
研究生(外文):Chih-Yi Yeh
論文名稱:考慮在電源雜訊環境下休眠電晶體置放之低功率平面規劃
論文名稱(外文):Floorplanning with Sleep Transistors Insertion in the Presence of Power Supply Noise for Low Power
指導教授:陳宏明陳宏明引用關係
指導教授(外文):Hung-Ming Chen
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:95
語文別:英文
論文頁數:30
中文關鍵詞:低功率電源雜訊平面規劃休眠電晶體
外文關鍵詞:low powerpower supply noisefloorplansleep transitstor
相關次數:
  • 被引用被引用:0
  • 點閱點閱:114
  • 評分評分:
  • 下載下載:9
  • 收藏至我的研究室書目清單書目收藏:0
近來隨著製程不斷的進步,晶片的面積與工作頻率都能做得很好,而
低功率卻成為現今最熱門的問題。高臨界電壓的電晶體由於其特性被
用來限制電路的漏電流現象,來減少電路在非工作時間裡所損耗的功
率,這種特殊的電晶體我們稱為休眠電晶體。然而以往休眠電晶體只
應用在極少的地方上,直到最近才被重視而成為相當熱門的研究話
題。本論文則是研究如何決定在哪些電路裡插入電晶體才會節省到功
率;以及在做平面規劃時,如何將休眠電晶體所需要的面積考慮進
去。實驗結果顯示我們的方法是有效的,可以得到一個考慮電源雜
訊,並放置休眠電晶體的低功率平面規劃。
As the technology scales, the chip area and the working frequency can be done very well. However, low power becomes the most hot topic. High threshold voltage transistors are used to limit the leakage current to reduce the unnecessary power when the circuit is idle. And this high threshold voltage transistors are called sleep transistors. However sleep transistor is used in few application in the past, and now it becomes a hot topic. This thesis research how to decide which modules are really need to be inserting sleep transistors, and how to design enough area for sleep
transistor when we do the floorplan. The experimental results show our method can work, and we can get a low power floorplan with sleep transistor insertion in the
presence of power supply noise.
Abstract (Chinese) i
Abstract (English) ii
Contents iii
List of Tables v
List of Figures viii
Chapter 1 Introduction 1
1.1 Our Contribution 2
1.2 Organization of this Thesis 2
Chapter 2 Preliminaries 3
2.1 Sleep Transistor 3
2.1.1 Sleep Transistor Insertion and Sizing 3
2.1.2 Power Supply Noise Effect on Sleep Transistor 4
2.1.3 Cost Evaluation on Sleep Transistor Insertion 5
2.2 Power Supply Distribution and Power Supply Noise Calculation 6
2.3 Floorplan Representations 8
2.3.1 Review of the Sequence Pair Representation 8
2.3.2 Review of the B*-tree Representation 9
2.4 Problem Formulation 11
Chapter 3 Methodology for Integrating Floorplann and Sleep Transistor Sizing
in the Presence of Power Supply Noise 12
3.1 Power Evaluation 12
3.2 Sequence Pair Packing 13
3.3 B*-tree Packing 16
Chapter 4 Experimental Results 22
4.1 Power Analysis Results 22
4.2 Floorplan Results 23
Chapter 5 Conclusion 27
Bibliography 28
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[2] Murata, Fujiyoshi, Nakatake, and Kajitani. “Rectangle-Packing Based Module Placement”. In Proceedings IEEE/ACM International Conference on Computer-Aided Design, 1995.
[3] Xiaoping Tang and D.F. Wang. “FAST-SP:A Fast Algorithm for Block Placement basced on Sequence Pair”. In Proceedings IEEE Asia and South Pacific Design Automation Conference, 2001.
[4] Y.-C. Chang, Y.-W. Chang, G.-M. Wu, and S. W. Wu. “B*-Trees: A new representation for non-slicing floorplans”. In Proceedings IEEE/ACM Design Automation Conference, pages 458–463, April 2000.
[5] Guang-Ming Wu, Yun-Chih Chang, and Yao-Wen Chang. “Rectilinear Block Placement Using B*-Trees”. In ACM Trans. on Design Automation of Electronic Systems, April 2003.
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[7] Benton H. Calhoun, Frank A. Honor´e, and Anaatha P. Chandrakasan. “A Leakage Reduction Methodology for Distributed MTCMOS”. In IEEE Journal of Solid State Circuit, May 2004.
[8] Vishal Khandelwal and Ankur Srivastava. “Leakage Control Through Fine-Grained Placement and Sizing of Sleep Transistors”. In Proceedings IEEE/ACM International Conference on Computer-Aided Design, 2004.
[9] Anand Ramalingam, Bin Zhang, Anirudh Degan, and Daid Z. Pan. “Sleep Transistor Sizing Using Timing Criticality and Temporal Currents”. In Proceedings IEEE Asia and South Pacific Design Automation Conference, 2005.
[10] Changbo Long, and Lei He. “Distributed Sleep Transistor Network for Power Reduction”. In IEEE Transactions on Very Large Scale Integration (VLSI)
Systems, September 2004.
[11] Pietro Babighian, Luca Benini, Alberto Macii, and Enrico Macii. “Post-Layout Leakage Power Minimization Based on Distributed Sleep Transistor Insertion”.
In ProceedingsInternational Symposium on Low Power Electronics and Design, 2004.
[12] Ramaprasath Vilangudipitchai and Poras T. Balsara. “Decap Aware Sleep Transistor Design”. In Proceedings of the 2004 IEEE Dallas/CAS Workshop Implementation of High Performance Circuits, pages 171–175, 2004.
[13] Ramaprasath Vilangudipitchai and Poras T. Balsara. “Power Switch Network Design for MTCMOS”. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2005.
[14] Afshin Abdollahi, Farzan Fallah, and Massoud Pedram. “An Effective Power Mode Transition Technique in MTCMOS Circuit”. In Proceedings IEEE/ACM Design Automation Conference, 2005.
[15] Kaijian Shi. “Dual threshold voltages and power-gating design flows offer good results”. In EDN, February 2006.
[16] Changbo Long, Jinjun Xiong, and Lei He. “On Optimal physical Synthesis of Sleep Transistors”. In Proceedings International Symposium on Physical Design, 2004.
[17] Magnus Sj¨alander, Mindaugas Drazdziulis, Per Larsson-Edefors, and Henrik Eriksson. “A Low-Leakage Twin- Precision Multiplier Using Reconfigurable Power Gating”. In Proceedings Internationl Symposium on Circuits and Systems,
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[18] Narendra Vallepalli, YihWang, B. Zheng, Kevin Zhang, Uddalak Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray and Mark Bohr. “SRAM Design on 65-nm CMOS Technologh With Dynamic Sleep Transistor for Leakage
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